1 /*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_damage_helper.h>
28 #include <drm/drm_fourcc.h>
29
30 #include "virtgpu_drv.h"
31
32 static const uint32_t virtio_gpu_formats[] = {
33 DRM_FORMAT_XRGB8888,
34 DRM_FORMAT_ARGB8888,
35 DRM_FORMAT_BGRX8888,
36 DRM_FORMAT_BGRA8888,
37 DRM_FORMAT_RGBX8888,
38 DRM_FORMAT_RGBA8888,
39 DRM_FORMAT_XBGR8888,
40 DRM_FORMAT_ABGR8888,
41 };
42
43 static const uint32_t virtio_gpu_cursor_formats[] = {
44 DRM_FORMAT_HOST_ARGB8888,
45 };
46
virtio_gpu_translate_format(uint32_t drm_fourcc)47 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
48 {
49 uint32_t format;
50
51 switch (drm_fourcc) {
52 #ifdef __BIG_ENDIAN
53 case DRM_FORMAT_XRGB8888:
54 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
55 break;
56 case DRM_FORMAT_ARGB8888:
57 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
58 break;
59 case DRM_FORMAT_BGRX8888:
60 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
61 break;
62 case DRM_FORMAT_BGRA8888:
63 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
64 break;
65 case DRM_FORMAT_RGBX8888:
66 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
67 break;
68 case DRM_FORMAT_RGBA8888:
69 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
70 break;
71 case DRM_FORMAT_XBGR8888:
72 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
73 break;
74 case DRM_FORMAT_ABGR8888:
75 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
76 break;
77 #else
78 case DRM_FORMAT_XRGB8888:
79 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
80 break;
81 case DRM_FORMAT_ARGB8888:
82 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
83 break;
84 case DRM_FORMAT_BGRX8888:
85 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
86 break;
87 case DRM_FORMAT_BGRA8888:
88 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
89 break;
90 case DRM_FORMAT_RGBX8888:
91 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
92 break;
93 case DRM_FORMAT_RGBA8888:
94 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
95 break;
96 case DRM_FORMAT_XBGR8888:
97 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
98 break;
99 case DRM_FORMAT_ABGR8888:
100 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
101 break;
102 #endif
103 default:
104 /*
105 * This should not happen, we handle everything listed
106 * in virtio_gpu_formats[].
107 */
108 format = 0;
109 break;
110 }
111 WARN_ON(format == 0);
112 return format;
113 }
114
115 static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
116 .update_plane = drm_atomic_helper_update_plane,
117 .disable_plane = drm_atomic_helper_disable_plane,
118 .reset = drm_atomic_helper_plane_reset,
119 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
120 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
121 };
122
virtio_gpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)123 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
124 struct drm_atomic_state *state)
125 {
126 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
127 plane);
128 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
129 struct drm_crtc_state *crtc_state;
130 int ret;
131
132 if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
133 return 0;
134
135 crtc_state = drm_atomic_get_crtc_state(state,
136 new_plane_state->crtc);
137 if (IS_ERR(crtc_state))
138 return PTR_ERR(crtc_state);
139
140 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
141 DRM_PLANE_NO_SCALING,
142 DRM_PLANE_NO_SCALING,
143 is_cursor, true);
144 return ret;
145 }
146
virtio_gpu_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)147 static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
148 struct drm_plane_state *state,
149 struct drm_rect *rect)
150 {
151 struct virtio_gpu_object *bo =
152 gem_to_virtio_gpu_obj(state->fb->obj[0]);
153 struct virtio_gpu_object_array *objs;
154 uint32_t w = rect->x2 - rect->x1;
155 uint32_t h = rect->y2 - rect->y1;
156 uint32_t x = rect->x1;
157 uint32_t y = rect->y1;
158 uint32_t off = x * state->fb->format->cpp[0] +
159 y * state->fb->pitches[0];
160
161 objs = virtio_gpu_array_alloc(1);
162 if (!objs)
163 return;
164 virtio_gpu_array_add_obj(objs, &bo->base.base);
165
166 virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
167 objs, NULL);
168 }
169
virtio_gpu_resource_flush(struct drm_plane * plane,uint32_t x,uint32_t y,uint32_t width,uint32_t height)170 static void virtio_gpu_resource_flush(struct drm_plane *plane,
171 uint32_t x, uint32_t y,
172 uint32_t width, uint32_t height)
173 {
174 struct drm_device *dev = plane->dev;
175 struct virtio_gpu_device *vgdev = dev->dev_private;
176 struct virtio_gpu_framebuffer *vgfb;
177 struct virtio_gpu_object *bo;
178
179 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
180 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
181 if (vgfb->fence) {
182 struct virtio_gpu_object_array *objs;
183
184 objs = virtio_gpu_array_alloc(1);
185 if (!objs)
186 return;
187 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
188 virtio_gpu_array_lock_resv(objs);
189 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
190 width, height, objs, vgfb->fence);
191 virtio_gpu_notify(vgdev);
192
193 dma_fence_wait_timeout(&vgfb->fence->f, true,
194 msecs_to_jiffies(50));
195 dma_fence_put(&vgfb->fence->f);
196 vgfb->fence = NULL;
197 } else {
198 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
199 width, height, NULL, NULL);
200 virtio_gpu_notify(vgdev);
201 }
202 }
203
virtio_gpu_primary_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)204 static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
205 struct drm_atomic_state *state)
206 {
207 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
208 plane);
209 struct drm_device *dev = plane->dev;
210 struct virtio_gpu_device *vgdev = dev->dev_private;
211 struct virtio_gpu_output *output = NULL;
212 struct virtio_gpu_object *bo;
213 struct drm_rect rect;
214
215 if (plane->state->crtc)
216 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
217 if (old_state->crtc)
218 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
219 if (WARN_ON(!output))
220 return;
221
222 if (!plane->state->fb || !output->crtc.state->active) {
223 DRM_DEBUG("nofb\n");
224 virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
225 plane->state->src_w >> 16,
226 plane->state->src_h >> 16,
227 0, 0);
228 virtio_gpu_notify(vgdev);
229 return;
230 }
231
232 if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
233 return;
234
235 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
236 if (bo->dumb)
237 virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
238
239 if (plane->state->fb != old_state->fb ||
240 plane->state->src_w != old_state->src_w ||
241 plane->state->src_h != old_state->src_h ||
242 plane->state->src_x != old_state->src_x ||
243 plane->state->src_y != old_state->src_y ||
244 output->needs_modeset) {
245 output->needs_modeset = false;
246 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
247 bo->hw_res_handle,
248 plane->state->crtc_w, plane->state->crtc_h,
249 plane->state->crtc_x, plane->state->crtc_y,
250 plane->state->src_w >> 16,
251 plane->state->src_h >> 16,
252 plane->state->src_x >> 16,
253 plane->state->src_y >> 16);
254
255 if (bo->host3d_blob || bo->guest_blob) {
256 virtio_gpu_cmd_set_scanout_blob
257 (vgdev, output->index, bo,
258 plane->state->fb,
259 plane->state->src_w >> 16,
260 plane->state->src_h >> 16,
261 plane->state->src_x >> 16,
262 plane->state->src_y >> 16);
263 } else {
264 virtio_gpu_cmd_set_scanout(vgdev, output->index,
265 bo->hw_res_handle,
266 plane->state->src_w >> 16,
267 plane->state->src_h >> 16,
268 plane->state->src_x >> 16,
269 plane->state->src_y >> 16);
270 }
271 }
272
273 virtio_gpu_resource_flush(plane,
274 rect.x1,
275 rect.y1,
276 rect.x2 - rect.x1,
277 rect.y2 - rect.y1);
278 }
279
virtio_gpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)280 static int virtio_gpu_plane_prepare_fb(struct drm_plane *plane,
281 struct drm_plane_state *new_state)
282 {
283 struct drm_device *dev = plane->dev;
284 struct virtio_gpu_device *vgdev = dev->dev_private;
285 struct virtio_gpu_framebuffer *vgfb;
286 struct virtio_gpu_object *bo;
287
288 if (!new_state->fb)
289 return 0;
290
291 vgfb = to_virtio_gpu_framebuffer(new_state->fb);
292 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
293 if (!bo || (plane->type == DRM_PLANE_TYPE_PRIMARY && !bo->guest_blob))
294 return 0;
295
296 if (bo->dumb && (plane->state->fb != new_state->fb)) {
297 vgfb->fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context,
298 0);
299 if (!vgfb->fence)
300 return -ENOMEM;
301 }
302
303 return 0;
304 }
305
virtio_gpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)306 static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane,
307 struct drm_plane_state *state)
308 {
309 struct virtio_gpu_framebuffer *vgfb;
310
311 if (!state->fb)
312 return;
313
314 vgfb = to_virtio_gpu_framebuffer(state->fb);
315 if (vgfb->fence) {
316 dma_fence_put(&vgfb->fence->f);
317 vgfb->fence = NULL;
318 }
319 }
320
virtio_gpu_cursor_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)321 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
322 struct drm_atomic_state *state)
323 {
324 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
325 plane);
326 struct drm_device *dev = plane->dev;
327 struct virtio_gpu_device *vgdev = dev->dev_private;
328 struct virtio_gpu_output *output = NULL;
329 struct virtio_gpu_framebuffer *vgfb;
330 struct virtio_gpu_object *bo = NULL;
331 uint32_t handle;
332
333 if (plane->state->crtc)
334 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
335 if (old_state->crtc)
336 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
337 if (WARN_ON(!output))
338 return;
339
340 if (plane->state->fb) {
341 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
342 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
343 handle = bo->hw_res_handle;
344 } else {
345 handle = 0;
346 }
347
348 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
349 /* new cursor -- update & wait */
350 struct virtio_gpu_object_array *objs;
351
352 objs = virtio_gpu_array_alloc(1);
353 if (!objs)
354 return;
355 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
356 virtio_gpu_array_lock_resv(objs);
357 virtio_gpu_cmd_transfer_to_host_2d
358 (vgdev, 0,
359 plane->state->crtc_w,
360 plane->state->crtc_h,
361 0, 0, objs, vgfb->fence);
362 virtio_gpu_notify(vgdev);
363 dma_fence_wait(&vgfb->fence->f, true);
364 dma_fence_put(&vgfb->fence->f);
365 vgfb->fence = NULL;
366 }
367
368 if (plane->state->fb != old_state->fb) {
369 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
370 plane->state->crtc_x,
371 plane->state->crtc_y,
372 plane->state->fb ? plane->state->fb->hot_x : 0,
373 plane->state->fb ? plane->state->fb->hot_y : 0);
374 output->cursor.hdr.type =
375 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
376 output->cursor.resource_id = cpu_to_le32(handle);
377 if (plane->state->fb) {
378 output->cursor.hot_x =
379 cpu_to_le32(plane->state->fb->hot_x);
380 output->cursor.hot_y =
381 cpu_to_le32(plane->state->fb->hot_y);
382 } else {
383 output->cursor.hot_x = cpu_to_le32(0);
384 output->cursor.hot_y = cpu_to_le32(0);
385 }
386 } else {
387 DRM_DEBUG("move +%d+%d\n",
388 plane->state->crtc_x,
389 plane->state->crtc_y);
390 output->cursor.hdr.type =
391 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
392 }
393 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
394 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
395 virtio_gpu_cursor_ping(vgdev, output);
396 }
397
398 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
399 .prepare_fb = virtio_gpu_plane_prepare_fb,
400 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
401 .atomic_check = virtio_gpu_plane_atomic_check,
402 .atomic_update = virtio_gpu_primary_plane_update,
403 };
404
405 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
406 .prepare_fb = virtio_gpu_plane_prepare_fb,
407 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
408 .atomic_check = virtio_gpu_plane_atomic_check,
409 .atomic_update = virtio_gpu_cursor_plane_update,
410 };
411
virtio_gpu_plane_init(struct virtio_gpu_device * vgdev,enum drm_plane_type type,int index)412 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
413 enum drm_plane_type type,
414 int index)
415 {
416 struct drm_device *dev = vgdev->ddev;
417 const struct drm_plane_helper_funcs *funcs;
418 struct drm_plane *plane;
419 const uint32_t *formats;
420 int nformats;
421
422 if (type == DRM_PLANE_TYPE_CURSOR) {
423 formats = virtio_gpu_cursor_formats;
424 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
425 funcs = &virtio_gpu_cursor_helper_funcs;
426 } else {
427 formats = virtio_gpu_formats;
428 nformats = ARRAY_SIZE(virtio_gpu_formats);
429 funcs = &virtio_gpu_primary_helper_funcs;
430 }
431
432 plane = drmm_universal_plane_alloc(dev, struct drm_plane, dev,
433 1 << index, &virtio_gpu_plane_funcs,
434 formats, nformats, NULL, type, NULL);
435 if (IS_ERR(plane))
436 return plane;
437
438 drm_plane_helper_add(plane, funcs);
439 return plane;
440 }
441