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/Documentation/translations/zh_CN/driver-api/gpio/
Dlegacy.rst5 :Original: Documentation/driver-api/gpio/legacy.rst
26 "通用输入/输出口"(GPIO)是一个灵活的由软件控制的数字信号。他们可
29 “球珠”的一个位。电路板原理图显示了 GPIO 与外部硬件的连接关系。
32 片上系统 (SOC) 处理器对 GPIO 有很大的依赖。在某些情况下,每个
33 非专用引脚都可配置为 GPIO,且大多数芯片都最少有一些 GPIO。
34 可编程逻辑器件(类似 FPGA) 可以方便地提供 GPIO。像电源管理和
37 芯片。大多数 PC 的南桥有一些拥有 GPIO 能力的引脚 (只有BIOS
40 GPIO 的实际功能因系统而异。通常用法有:
47 “线与”的情况(以支持双向信号)是非常有用的。GPIO 控制器可能有输入
53 - 通常一个 GPIO 根据不同产品电路板的需求,可以配置为输入或输出,也有仅
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/Documentation/translations/zh_TW/
Dgpio.txt1 Chinese translated version of Documentation/admin-guide/gpio
13 Documentation/admin-guide/gpio 的繁體中文翻譯
27 GPIO 接口
37 "通用輸入/輸出口"(GPIO)是一個靈活的由軟體控制的數位訊號。他們可
40 「球珠」的一個位。電路板原理圖顯示了 GPIO 與外部硬體的連接關係。
43 片上系統 (SOC) 處理器對 GPIO 有很大的依賴。在某些情況下,每個
44 非專用引腳都可配置爲 GPIO,且大多數晶片都最少有一些 GPIO。
45 可編程邏輯器件(類似 FPGA) 可以方便地提供 GPIO。像電源管理和
48 晶片。大多數 PC 的南橋有一些擁有 GPIO 能力的引腳 (只有BIOS
51 GPIO 的實際功能因系統而異。通常用法有:
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/Documentation/devicetree/bindings/pinctrl/
Dqcom,pmic-gpio.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml#
7 title: Qualcomm PMIC GPIO block
13 This binding describes the GPIO block(s) found in the 8xxx series of
20 - qcom,pm2250-gpio
21 - qcom,pm660-gpio
22 - qcom,pm660l-gpio
23 - qcom,pm6125-gpio
24 - qcom,pm6150-gpio
25 - qcom,pm6150l-gpio
26 - qcom,pm6350-gpio
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Dmarvell,armada-375-pinctrl.txt16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
18 mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
19 mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
20 mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
21 mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
22 mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk)
23 mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
24 mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
25 mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
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Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
34 - functions jtag, gpio
38 - functions sdio, gpio
42 - functions emmc, gpio
46 - functions pwm, led, gpio
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Dmarvell,armada-xp-pinctrl.txt21 mpp0 0 gpio, ge0(txclkout), lcd(d0)
22 mpp1 1 gpio, ge0(txd0), lcd(d1)
23 mpp2 2 gpio, ge0(txd1), lcd(d2)
24 mpp3 3 gpio, ge0(txd2), lcd(d3)
25 mpp4 4 gpio, ge0(txd3), lcd(d4)
26 mpp5 5 gpio, ge0(txctl), lcd(d5)
27 mpp6 6 gpio, ge0(rxd0), lcd(d6)
28 mpp7 7 gpio, ge0(rxd1), lcd(d7)
29 mpp8 8 gpio, ge0(rxd2), lcd(d8)
30 mpp9 9 gpio, ge0(rxd3), lcd(d9)
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Dmarvell,kirkwood-pinctrl.txt24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
32 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
34 mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
40 mpp13 13 gpio, sdio(cmd), uart1(txd)
41 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
42 mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
43 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
44 mpp17 17 gpio, sdio(d3)
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Dmarvell,orion-pinctrl.txt24 mpp0 0 pcie(rstout), pci(req2), gpio
25 mpp1 1 gpio, pci(gnt2)
26 mpp2 2 gpio, pci(req3), pci-1(pme)
27 mpp3 3 gpio, pci(gnt3)
28 mpp4 4 gpio, pci(req4)
29 mpp5 5 gpio, pci(gnt4)
30 mpp6 6 gpio, pci(req5), pci-1(clk)
31 mpp7 7 gpio, pci(gnt5), pci-1(clk)
32 mpp8 8 gpio, ge(col)
33 mpp9 9 gpio, ge(rxerr)
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Dbrcm,iproc-gpio.txt1 Broadcom iProc GPIO/PINCONF Controller
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
25 GPIO/PINCONF controller registers
28 Total number of in-use slots in GPIO controller
30 - #gpio-cells:
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Dmarvell,armada-39x-pinctrl.txt18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
21 mpp3 3 gpio, i2c0(sda)
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
24 mpp6 6 gpio, dev(cs3), xsmi(mdio)
25 mpp7 7 gpio, dev(ad9), xsmi(mdc)
26 mpp8 8 gpio, dev(ad10), ptp(trig)
27 mpp9 9 gpio, dev(ad11), ptp(clk)
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Dmarvell,armada-38x-pinctrl.txt18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
21 mpp3 3 gpio, i2c0(sda)
22 mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
23 mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
24 mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3)
25 mpp7 7 gpio, ge0(txd0), dev(ad9)
26 mpp8 8 gpio, ge0(txd1), dev(ad10)
27 mpp9 9 gpio, ge0(txd2), dev(ad11)
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/Documentation/devicetree/bindings/gpio/
Dfsl-imx-gpio.yaml4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
7 title: Freescale i.MX/MXC GPIO controller
16 - fsl,imx1-gpio
17 - fsl,imx21-gpio
18 - fsl,imx31-gpio
19 - fsl,imx35-gpio
20 - fsl,imx7d-gpio
22 - const: fsl,imx35-gpio
23 - const: fsl,imx31-gpio
26 - fsl,imx50-gpio
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Drenesas,rcar-gpio.yaml4 $id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml#
7 title: Renesas R-Car General-Purpose Input/Output Ports (GPIO)
17 - renesas,gpio-r8a7778 # R-Car M1
18 - renesas,gpio-r8a7779 # R-Car H1
19 - const: renesas,rcar-gen1-gpio # R-Car Gen1
23 - renesas,gpio-r8a7742 # RZ/G1H
24 - renesas,gpio-r8a7743 # RZ/G1M
25 - renesas,gpio-r8a7744 # RZ/G1N
26 - renesas,gpio-r8a7745 # RZ/G1E
27 - renesas,gpio-r8a77470 # RZ/G1C
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Dnxp,lpc1850-gpio.txt1 NXP LPC18xx/43xx GPIO controller Device Tree Bindings
5 - compatible : Should be "nxp,lpc1850-gpio"
6 - reg : List of addresses and lengths of the GPIO controller
8 - reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
9 "gpio-gpoup1-ic"
10 - clocks : Phandle and clock specifier pair for GPIO controller
11 - resets : Phandle and reset specifier pair for GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller
13 - #gpio-cells : Should be two:
14 - The first cell is the GPIO line number
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D8xxx_gpio.txt1 GPIO controllers on MPC8xxx SoCs
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
8 See bindings/gpio/gpio.txt for details of how to specify GPIO
11 The GPIO module usually is connected to the SoC's internal interrupt
13 interrupt client nodes section) for details how to specify this GPIO
16 The GPIO module may serve as another interrupt controller (cascaded to
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
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Dgpio-mxs.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
7 title: Freescale MXS GPIO controller
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
35 "gpio@[0-9]+$":
40 - fsl,imx23-gpio
41 - fsl,imx28-gpio
55 "#gpio-cells":
58 gpio-controller: true
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Dgpio.txt1 Specifying GPIO information for devices
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
27 gpio-controller;
28 #gpio-cells = <2>;
37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
38 a local offset to the GPIO line and the second cell represent consumer flags,
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Dmrvl-gpio.yaml4 $id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
7 title: Marvell PXA GPIO controller
20 - intel,pxa25x-gpio
21 - intel,pxa26x-gpio
22 - intel,pxa27x-gpio
23 - intel,pxa3xx-gpio
39 - marvell,mmp-gpio
40 - marvell,mmp2-gpio
51 pattern: '^gpio@[0-9a-f]+$'
55 - intel,pxa25x-gpio
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Dbrcm,bcm6345-gpio.yaml4 $id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
7 title: Broadcom BCM6345 GPIO controller
14 Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.
19 BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
21 BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
24 and dirout registers, where GPIO state can be read and/or written, and the
30 - brcm,bcm6318-gpio
31 - brcm,bcm6328-gpio
32 - brcm,bcm6345-gpio
33 - brcm,bcm6358-gpio
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Dgpio-vf610.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
7 title: Freescale VF610 PORT/GPIO module
13 The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
17 Note: Each GPIO port should have an alias correctly numbered in "aliases"
23 - const: fsl,vf610-gpio
25 - const: fsl,imx7ulp-gpio
26 - const: fsl,vf610-gpio
29 - fsl,imx93-gpio
30 - fsl,imx8ulp-gpio
31 - const: fsl,imx7ulp-gpio
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Dgpio-zynq.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
7 title: Xilinx Zynq GPIO controller
15 - xlnx,zynq-gpio-1.0
16 - xlnx,zynqmp-gpio-1.0
17 - xlnx,versal-gpio-1.0
18 - xlnx,pmc-gpio-1.0
23 "#gpio-cells":
29 gpio-controller: true
31 gpio-line-names:
32 description: strings describing the names of each gpio line
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Dnvidia,tegra186-gpio.yaml4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
20 The Tegra186 GPIO controller allows software to set the IO direction of,
21 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
26 GPIO register set. These registers exist in a single contiguous block
28 features available, varies between the different GPIO controllers.
31 Code that wishes to configure access to the GPIO registers needs access
33 GPIO data does not need access to these registers.
35 b) GPIO registers, which allow manipulation of the GPIO signals. In some
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/Documentation/admin-guide/gpio/
Dgpio-sim.rst3 Configfs GPIO Simulator
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
8 using the standard GPIO character device interface as well as manipulated
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
27 **Attribute:** ``/config/gpio-sim/gpio-device/dev_name``
29 **Attribute:** ``/config/gpio-sim/gpio-device/live``
31 This is a directory representing a GPIO platform device. The ``'dev_name'``
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/Documentation/driver-api/gpio/
Ddrivers-on-gpio.rst2 Subsystem drivers using GPIO
5 Note that standard kernel drivers exist for common GPIO tasks and will provide
10 - leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
13 - ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
14 i.e. a LED will turn on/off in response to a GPIO line going high or low
15 (and that LED may in turn use the leds-gpio as per above).
17 - gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
20 - gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
21 GPIO line cannot generate interrupts, so it needs to be periodically polled
26 mouse cable and connect the wires to GPIO lines or solder a mouse connector
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/Documentation/devicetree/bindings/fsi/
Dfsi-master-gpio.txt1 Device-tree bindings for gpio-based FSI master driver
5 - compatible = "fsi-master-gpio";
6 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
7 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
10 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
11 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
12 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
14 - no-gpio-delays; : Don't add extra delays between GPIO
16 GPIO block is running at a low enough
22 compatible = "fsi-master-gpio", "fsi-master";
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