1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * caam - Freescale FSL CAAM support for crypto API
4 *
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 * Copyright 2016-2019 NXP
7 *
8 * Based on talitos crypto API driver.
9 *
10 * relationship of job descriptors to shared descriptors (SteveC Dec 10 2008):
11 *
12 * --------------- ---------------
13 * | JobDesc #1 |-------------------->| ShareDesc |
14 * | *(packet 1) | | (PDB) |
15 * --------------- |------------->| (hashKey) |
16 * . | | (cipherKey) |
17 * . | |-------->| (operation) |
18 * --------------- | | ---------------
19 * | JobDesc #2 |------| |
20 * | *(packet 2) | |
21 * --------------- |
22 * . |
23 * . |
24 * --------------- |
25 * | JobDesc #3 |------------
26 * | *(packet 3) |
27 * ---------------
28 *
29 * The SharedDesc never changes for a connection unless rekeyed, but
30 * each packet will likely be in a different place. So all we need
31 * to know to process the packet is where the input is, where the
32 * output goes, and what context we want to process with. Context is
33 * in the SharedDesc, packet references in the JobDesc.
34 *
35 * So, a job desc looks like:
36 *
37 * ---------------------
38 * | Header |
39 * | ShareDesc Pointer |
40 * | SEQ_OUT_PTR |
41 * | (output buffer) |
42 * | (output length) |
43 * | SEQ_IN_PTR |
44 * | (input buffer) |
45 * | (input length) |
46 * ---------------------
47 */
48
49 #include "compat.h"
50
51 #include "regs.h"
52 #include "intern.h"
53 #include "desc_constr.h"
54 #include "jr.h"
55 #include "error.h"
56 #include "sg_sw_sec4.h"
57 #include "key_gen.h"
58 #include "caamalg_desc.h"
59 #include <crypto/engine.h>
60 #include <crypto/xts.h>
61 #include <asm/unaligned.h>
62
63 /*
64 * crypto alg
65 */
66 #define CAAM_CRA_PRIORITY 3000
67 /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
68 #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
69 CTR_RFC3686_NONCE_SIZE + \
70 SHA512_DIGEST_SIZE * 2)
71
72 #define AEAD_DESC_JOB_IO_LEN (DESC_JOB_IO_LEN + CAAM_CMD_SZ * 2)
73 #define GCM_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + \
74 CAAM_CMD_SZ * 4)
75 #define AUTHENC_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + \
76 CAAM_CMD_SZ * 5)
77
78 #define CHACHAPOLY_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + CAAM_CMD_SZ * 6)
79
80 #define DESC_MAX_USED_BYTES (CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN_MIN)
81 #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
82
83 struct caam_alg_entry {
84 int class1_alg_type;
85 int class2_alg_type;
86 bool rfc3686;
87 bool geniv;
88 bool nodkp;
89 };
90
91 struct caam_aead_alg {
92 struct aead_alg aead;
93 struct caam_alg_entry caam;
94 bool registered;
95 };
96
97 struct caam_skcipher_alg {
98 struct skcipher_alg skcipher;
99 struct caam_alg_entry caam;
100 bool registered;
101 };
102
103 /*
104 * per-session context
105 */
106 struct caam_ctx {
107 struct crypto_engine_ctx enginectx;
108 u32 sh_desc_enc[DESC_MAX_USED_LEN];
109 u32 sh_desc_dec[DESC_MAX_USED_LEN];
110 u8 key[CAAM_MAX_KEY_SIZE];
111 dma_addr_t sh_desc_enc_dma;
112 dma_addr_t sh_desc_dec_dma;
113 dma_addr_t key_dma;
114 enum dma_data_direction dir;
115 struct device *jrdev;
116 struct alginfo adata;
117 struct alginfo cdata;
118 unsigned int authsize;
119 bool xts_key_fallback;
120 struct crypto_skcipher *fallback;
121 };
122
123 struct caam_skcipher_req_ctx {
124 struct skcipher_edesc *edesc;
125 struct skcipher_request fallback_req;
126 };
127
128 struct caam_aead_req_ctx {
129 struct aead_edesc *edesc;
130 };
131
aead_null_set_sh_desc(struct crypto_aead * aead)132 static int aead_null_set_sh_desc(struct crypto_aead *aead)
133 {
134 struct caam_ctx *ctx = crypto_aead_ctx(aead);
135 struct device *jrdev = ctx->jrdev;
136 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
137 u32 *desc;
138 int rem_bytes = CAAM_DESC_BYTES_MAX - AEAD_DESC_JOB_IO_LEN -
139 ctx->adata.keylen_pad;
140
141 /*
142 * Job Descriptor and Shared Descriptors
143 * must all fit into the 64-word Descriptor h/w Buffer
144 */
145 if (rem_bytes >= DESC_AEAD_NULL_ENC_LEN) {
146 ctx->adata.key_inline = true;
147 ctx->adata.key_virt = ctx->key;
148 } else {
149 ctx->adata.key_inline = false;
150 ctx->adata.key_dma = ctx->key_dma;
151 }
152
153 /* aead_encrypt shared descriptor */
154 desc = ctx->sh_desc_enc;
155 cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize,
156 ctrlpriv->era);
157 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
158 desc_bytes(desc), ctx->dir);
159
160 /*
161 * Job Descriptor and Shared Descriptors
162 * must all fit into the 64-word Descriptor h/w Buffer
163 */
164 if (rem_bytes >= DESC_AEAD_NULL_DEC_LEN) {
165 ctx->adata.key_inline = true;
166 ctx->adata.key_virt = ctx->key;
167 } else {
168 ctx->adata.key_inline = false;
169 ctx->adata.key_dma = ctx->key_dma;
170 }
171
172 /* aead_decrypt shared descriptor */
173 desc = ctx->sh_desc_dec;
174 cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize,
175 ctrlpriv->era);
176 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
177 desc_bytes(desc), ctx->dir);
178
179 return 0;
180 }
181
aead_set_sh_desc(struct crypto_aead * aead)182 static int aead_set_sh_desc(struct crypto_aead *aead)
183 {
184 struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
185 struct caam_aead_alg, aead);
186 unsigned int ivsize = crypto_aead_ivsize(aead);
187 struct caam_ctx *ctx = crypto_aead_ctx(aead);
188 struct device *jrdev = ctx->jrdev;
189 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
190 u32 ctx1_iv_off = 0;
191 u32 *desc, *nonce = NULL;
192 u32 inl_mask;
193 unsigned int data_len[2];
194 const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
195 OP_ALG_AAI_CTR_MOD128);
196 const bool is_rfc3686 = alg->caam.rfc3686;
197
198 if (!ctx->authsize)
199 return 0;
200
201 /* NULL encryption / decryption */
202 if (!ctx->cdata.keylen)
203 return aead_null_set_sh_desc(aead);
204
205 /*
206 * AES-CTR needs to load IV in CONTEXT1 reg
207 * at an offset of 128bits (16bytes)
208 * CONTEXT1[255:128] = IV
209 */
210 if (ctr_mode)
211 ctx1_iv_off = 16;
212
213 /*
214 * RFC3686 specific:
215 * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
216 */
217 if (is_rfc3686) {
218 ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
219 nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
220 ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
221 }
222
223 /*
224 * In case |user key| > |derived key|, using DKP<imm,imm>
225 * would result in invalid opcodes (last bytes of user key) in
226 * the resulting descriptor. Use DKP<ptr,imm> instead => both
227 * virtual and dma key addresses are needed.
228 */
229 ctx->adata.key_virt = ctx->key;
230 ctx->adata.key_dma = ctx->key_dma;
231
232 ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
233 ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
234
235 data_len[0] = ctx->adata.keylen_pad;
236 data_len[1] = ctx->cdata.keylen;
237
238 if (alg->caam.geniv)
239 goto skip_enc;
240
241 /*
242 * Job Descriptor and Shared Descriptors
243 * must all fit into the 64-word Descriptor h/w Buffer
244 */
245 if (desc_inline_query(DESC_AEAD_ENC_LEN +
246 (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
247 AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
248 ARRAY_SIZE(data_len)) < 0)
249 return -EINVAL;
250
251 ctx->adata.key_inline = !!(inl_mask & 1);
252 ctx->cdata.key_inline = !!(inl_mask & 2);
253
254 /* aead_encrypt shared descriptor */
255 desc = ctx->sh_desc_enc;
256 cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
257 ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
258 false, ctrlpriv->era);
259 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
260 desc_bytes(desc), ctx->dir);
261
262 skip_enc:
263 /*
264 * Job Descriptor and Shared Descriptors
265 * must all fit into the 64-word Descriptor h/w Buffer
266 */
267 if (desc_inline_query(DESC_AEAD_DEC_LEN +
268 (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
269 AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
270 ARRAY_SIZE(data_len)) < 0)
271 return -EINVAL;
272
273 ctx->adata.key_inline = !!(inl_mask & 1);
274 ctx->cdata.key_inline = !!(inl_mask & 2);
275
276 /* aead_decrypt shared descriptor */
277 desc = ctx->sh_desc_dec;
278 cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
279 ctx->authsize, alg->caam.geniv, is_rfc3686,
280 nonce, ctx1_iv_off, false, ctrlpriv->era);
281 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
282 desc_bytes(desc), ctx->dir);
283
284 if (!alg->caam.geniv)
285 goto skip_givenc;
286
287 /*
288 * Job Descriptor and Shared Descriptors
289 * must all fit into the 64-word Descriptor h/w Buffer
290 */
291 if (desc_inline_query(DESC_AEAD_GIVENC_LEN +
292 (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
293 AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
294 ARRAY_SIZE(data_len)) < 0)
295 return -EINVAL;
296
297 ctx->adata.key_inline = !!(inl_mask & 1);
298 ctx->cdata.key_inline = !!(inl_mask & 2);
299
300 /* aead_givencrypt shared descriptor */
301 desc = ctx->sh_desc_enc;
302 cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
303 ctx->authsize, is_rfc3686, nonce,
304 ctx1_iv_off, false, ctrlpriv->era);
305 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
306 desc_bytes(desc), ctx->dir);
307
308 skip_givenc:
309 return 0;
310 }
311
aead_setauthsize(struct crypto_aead * authenc,unsigned int authsize)312 static int aead_setauthsize(struct crypto_aead *authenc,
313 unsigned int authsize)
314 {
315 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
316
317 ctx->authsize = authsize;
318 aead_set_sh_desc(authenc);
319
320 return 0;
321 }
322
gcm_set_sh_desc(struct crypto_aead * aead)323 static int gcm_set_sh_desc(struct crypto_aead *aead)
324 {
325 struct caam_ctx *ctx = crypto_aead_ctx(aead);
326 struct device *jrdev = ctx->jrdev;
327 unsigned int ivsize = crypto_aead_ivsize(aead);
328 u32 *desc;
329 int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
330 ctx->cdata.keylen;
331
332 if (!ctx->cdata.keylen || !ctx->authsize)
333 return 0;
334
335 /*
336 * AES GCM encrypt shared descriptor
337 * Job Descriptor and Shared Descriptor
338 * must fit into the 64-word Descriptor h/w Buffer
339 */
340 if (rem_bytes >= DESC_GCM_ENC_LEN) {
341 ctx->cdata.key_inline = true;
342 ctx->cdata.key_virt = ctx->key;
343 } else {
344 ctx->cdata.key_inline = false;
345 ctx->cdata.key_dma = ctx->key_dma;
346 }
347
348 desc = ctx->sh_desc_enc;
349 cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
350 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
351 desc_bytes(desc), ctx->dir);
352
353 /*
354 * Job Descriptor and Shared Descriptors
355 * must all fit into the 64-word Descriptor h/w Buffer
356 */
357 if (rem_bytes >= DESC_GCM_DEC_LEN) {
358 ctx->cdata.key_inline = true;
359 ctx->cdata.key_virt = ctx->key;
360 } else {
361 ctx->cdata.key_inline = false;
362 ctx->cdata.key_dma = ctx->key_dma;
363 }
364
365 desc = ctx->sh_desc_dec;
366 cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
367 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
368 desc_bytes(desc), ctx->dir);
369
370 return 0;
371 }
372
gcm_setauthsize(struct crypto_aead * authenc,unsigned int authsize)373 static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
374 {
375 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
376 int err;
377
378 err = crypto_gcm_check_authsize(authsize);
379 if (err)
380 return err;
381
382 ctx->authsize = authsize;
383 gcm_set_sh_desc(authenc);
384
385 return 0;
386 }
387
rfc4106_set_sh_desc(struct crypto_aead * aead)388 static int rfc4106_set_sh_desc(struct crypto_aead *aead)
389 {
390 struct caam_ctx *ctx = crypto_aead_ctx(aead);
391 struct device *jrdev = ctx->jrdev;
392 unsigned int ivsize = crypto_aead_ivsize(aead);
393 u32 *desc;
394 int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
395 ctx->cdata.keylen;
396
397 if (!ctx->cdata.keylen || !ctx->authsize)
398 return 0;
399
400 /*
401 * RFC4106 encrypt shared descriptor
402 * Job Descriptor and Shared Descriptor
403 * must fit into the 64-word Descriptor h/w Buffer
404 */
405 if (rem_bytes >= DESC_RFC4106_ENC_LEN) {
406 ctx->cdata.key_inline = true;
407 ctx->cdata.key_virt = ctx->key;
408 } else {
409 ctx->cdata.key_inline = false;
410 ctx->cdata.key_dma = ctx->key_dma;
411 }
412
413 desc = ctx->sh_desc_enc;
414 cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
415 false);
416 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
417 desc_bytes(desc), ctx->dir);
418
419 /*
420 * Job Descriptor and Shared Descriptors
421 * must all fit into the 64-word Descriptor h/w Buffer
422 */
423 if (rem_bytes >= DESC_RFC4106_DEC_LEN) {
424 ctx->cdata.key_inline = true;
425 ctx->cdata.key_virt = ctx->key;
426 } else {
427 ctx->cdata.key_inline = false;
428 ctx->cdata.key_dma = ctx->key_dma;
429 }
430
431 desc = ctx->sh_desc_dec;
432 cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
433 false);
434 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
435 desc_bytes(desc), ctx->dir);
436
437 return 0;
438 }
439
rfc4106_setauthsize(struct crypto_aead * authenc,unsigned int authsize)440 static int rfc4106_setauthsize(struct crypto_aead *authenc,
441 unsigned int authsize)
442 {
443 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
444 int err;
445
446 err = crypto_rfc4106_check_authsize(authsize);
447 if (err)
448 return err;
449
450 ctx->authsize = authsize;
451 rfc4106_set_sh_desc(authenc);
452
453 return 0;
454 }
455
rfc4543_set_sh_desc(struct crypto_aead * aead)456 static int rfc4543_set_sh_desc(struct crypto_aead *aead)
457 {
458 struct caam_ctx *ctx = crypto_aead_ctx(aead);
459 struct device *jrdev = ctx->jrdev;
460 unsigned int ivsize = crypto_aead_ivsize(aead);
461 u32 *desc;
462 int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
463 ctx->cdata.keylen;
464
465 if (!ctx->cdata.keylen || !ctx->authsize)
466 return 0;
467
468 /*
469 * RFC4543 encrypt shared descriptor
470 * Job Descriptor and Shared Descriptor
471 * must fit into the 64-word Descriptor h/w Buffer
472 */
473 if (rem_bytes >= DESC_RFC4543_ENC_LEN) {
474 ctx->cdata.key_inline = true;
475 ctx->cdata.key_virt = ctx->key;
476 } else {
477 ctx->cdata.key_inline = false;
478 ctx->cdata.key_dma = ctx->key_dma;
479 }
480
481 desc = ctx->sh_desc_enc;
482 cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
483 false);
484 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
485 desc_bytes(desc), ctx->dir);
486
487 /*
488 * Job Descriptor and Shared Descriptors
489 * must all fit into the 64-word Descriptor h/w Buffer
490 */
491 if (rem_bytes >= DESC_RFC4543_DEC_LEN) {
492 ctx->cdata.key_inline = true;
493 ctx->cdata.key_virt = ctx->key;
494 } else {
495 ctx->cdata.key_inline = false;
496 ctx->cdata.key_dma = ctx->key_dma;
497 }
498
499 desc = ctx->sh_desc_dec;
500 cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
501 false);
502 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
503 desc_bytes(desc), ctx->dir);
504
505 return 0;
506 }
507
rfc4543_setauthsize(struct crypto_aead * authenc,unsigned int authsize)508 static int rfc4543_setauthsize(struct crypto_aead *authenc,
509 unsigned int authsize)
510 {
511 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
512
513 if (authsize != 16)
514 return -EINVAL;
515
516 ctx->authsize = authsize;
517 rfc4543_set_sh_desc(authenc);
518
519 return 0;
520 }
521
chachapoly_set_sh_desc(struct crypto_aead * aead)522 static int chachapoly_set_sh_desc(struct crypto_aead *aead)
523 {
524 struct caam_ctx *ctx = crypto_aead_ctx(aead);
525 struct device *jrdev = ctx->jrdev;
526 unsigned int ivsize = crypto_aead_ivsize(aead);
527 u32 *desc;
528
529 if (!ctx->cdata.keylen || !ctx->authsize)
530 return 0;
531
532 desc = ctx->sh_desc_enc;
533 cnstr_shdsc_chachapoly(desc, &ctx->cdata, &ctx->adata, ivsize,
534 ctx->authsize, true, false);
535 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
536 desc_bytes(desc), ctx->dir);
537
538 desc = ctx->sh_desc_dec;
539 cnstr_shdsc_chachapoly(desc, &ctx->cdata, &ctx->adata, ivsize,
540 ctx->authsize, false, false);
541 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
542 desc_bytes(desc), ctx->dir);
543
544 return 0;
545 }
546
chachapoly_setauthsize(struct crypto_aead * aead,unsigned int authsize)547 static int chachapoly_setauthsize(struct crypto_aead *aead,
548 unsigned int authsize)
549 {
550 struct caam_ctx *ctx = crypto_aead_ctx(aead);
551
552 if (authsize != POLY1305_DIGEST_SIZE)
553 return -EINVAL;
554
555 ctx->authsize = authsize;
556 return chachapoly_set_sh_desc(aead);
557 }
558
chachapoly_setkey(struct crypto_aead * aead,const u8 * key,unsigned int keylen)559 static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key,
560 unsigned int keylen)
561 {
562 struct caam_ctx *ctx = crypto_aead_ctx(aead);
563 unsigned int ivsize = crypto_aead_ivsize(aead);
564 unsigned int saltlen = CHACHAPOLY_IV_SIZE - ivsize;
565
566 if (keylen != CHACHA_KEY_SIZE + saltlen)
567 return -EINVAL;
568
569 memcpy(ctx->key, key, keylen);
570 ctx->cdata.key_virt = ctx->key;
571 ctx->cdata.keylen = keylen - saltlen;
572
573 return chachapoly_set_sh_desc(aead);
574 }
575
aead_setkey(struct crypto_aead * aead,const u8 * key,unsigned int keylen)576 static int aead_setkey(struct crypto_aead *aead,
577 const u8 *key, unsigned int keylen)
578 {
579 struct caam_ctx *ctx = crypto_aead_ctx(aead);
580 struct device *jrdev = ctx->jrdev;
581 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
582 struct crypto_authenc_keys keys;
583 int ret = 0;
584
585 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
586 goto badkey;
587
588 dev_dbg(jrdev, "keylen %d enckeylen %d authkeylen %d\n",
589 keys.authkeylen + keys.enckeylen, keys.enckeylen,
590 keys.authkeylen);
591 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
592 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
593
594 /*
595 * If DKP is supported, use it in the shared descriptor to generate
596 * the split key.
597 */
598 if (ctrlpriv->era >= 6) {
599 ctx->adata.keylen = keys.authkeylen;
600 ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
601 OP_ALG_ALGSEL_MASK);
602
603 if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
604 goto badkey;
605
606 memcpy(ctx->key, keys.authkey, keys.authkeylen);
607 memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
608 keys.enckeylen);
609 dma_sync_single_for_device(jrdev, ctx->key_dma,
610 ctx->adata.keylen_pad +
611 keys.enckeylen, ctx->dir);
612 goto skip_split_key;
613 }
614
615 ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, keys.authkey,
616 keys.authkeylen, CAAM_MAX_KEY_SIZE -
617 keys.enckeylen);
618 if (ret) {
619 goto badkey;
620 }
621
622 /* postpend encryption key to auth split key */
623 memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
624 dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
625 keys.enckeylen, ctx->dir);
626
627 print_hex_dump_debug("ctx.key@"__stringify(__LINE__)": ",
628 DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
629 ctx->adata.keylen_pad + keys.enckeylen, 1);
630
631 skip_split_key:
632 ctx->cdata.keylen = keys.enckeylen;
633 memzero_explicit(&keys, sizeof(keys));
634 return aead_set_sh_desc(aead);
635 badkey:
636 memzero_explicit(&keys, sizeof(keys));
637 return -EINVAL;
638 }
639
des3_aead_setkey(struct crypto_aead * aead,const u8 * key,unsigned int keylen)640 static int des3_aead_setkey(struct crypto_aead *aead, const u8 *key,
641 unsigned int keylen)
642 {
643 struct crypto_authenc_keys keys;
644 int err;
645
646 err = crypto_authenc_extractkeys(&keys, key, keylen);
647 if (unlikely(err))
648 return err;
649
650 err = verify_aead_des3_key(aead, keys.enckey, keys.enckeylen) ?:
651 aead_setkey(aead, key, keylen);
652
653 memzero_explicit(&keys, sizeof(keys));
654 return err;
655 }
656
gcm_setkey(struct crypto_aead * aead,const u8 * key,unsigned int keylen)657 static int gcm_setkey(struct crypto_aead *aead,
658 const u8 *key, unsigned int keylen)
659 {
660 struct caam_ctx *ctx = crypto_aead_ctx(aead);
661 struct device *jrdev = ctx->jrdev;
662 int err;
663
664 err = aes_check_keylen(keylen);
665 if (err)
666 return err;
667
668 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
669 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
670
671 memcpy(ctx->key, key, keylen);
672 dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, ctx->dir);
673 ctx->cdata.keylen = keylen;
674
675 return gcm_set_sh_desc(aead);
676 }
677
rfc4106_setkey(struct crypto_aead * aead,const u8 * key,unsigned int keylen)678 static int rfc4106_setkey(struct crypto_aead *aead,
679 const u8 *key, unsigned int keylen)
680 {
681 struct caam_ctx *ctx = crypto_aead_ctx(aead);
682 struct device *jrdev = ctx->jrdev;
683 int err;
684
685 err = aes_check_keylen(keylen - 4);
686 if (err)
687 return err;
688
689 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
690 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
691
692 memcpy(ctx->key, key, keylen);
693
694 /*
695 * The last four bytes of the key material are used as the salt value
696 * in the nonce. Update the AES key length.
697 */
698 ctx->cdata.keylen = keylen - 4;
699 dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
700 ctx->dir);
701 return rfc4106_set_sh_desc(aead);
702 }
703
rfc4543_setkey(struct crypto_aead * aead,const u8 * key,unsigned int keylen)704 static int rfc4543_setkey(struct crypto_aead *aead,
705 const u8 *key, unsigned int keylen)
706 {
707 struct caam_ctx *ctx = crypto_aead_ctx(aead);
708 struct device *jrdev = ctx->jrdev;
709 int err;
710
711 err = aes_check_keylen(keylen - 4);
712 if (err)
713 return err;
714
715 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
716 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
717
718 memcpy(ctx->key, key, keylen);
719
720 /*
721 * The last four bytes of the key material are used as the salt value
722 * in the nonce. Update the AES key length.
723 */
724 ctx->cdata.keylen = keylen - 4;
725 dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
726 ctx->dir);
727 return rfc4543_set_sh_desc(aead);
728 }
729
skcipher_setkey(struct crypto_skcipher * skcipher,const u8 * key,unsigned int keylen,const u32 ctx1_iv_off)730 static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
731 unsigned int keylen, const u32 ctx1_iv_off)
732 {
733 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
734 struct caam_skcipher_alg *alg =
735 container_of(crypto_skcipher_alg(skcipher), typeof(*alg),
736 skcipher);
737 struct device *jrdev = ctx->jrdev;
738 unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
739 u32 *desc;
740 const bool is_rfc3686 = alg->caam.rfc3686;
741
742 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
743 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
744
745 ctx->cdata.keylen = keylen;
746 ctx->cdata.key_virt = key;
747 ctx->cdata.key_inline = true;
748
749 /* skcipher_encrypt shared descriptor */
750 desc = ctx->sh_desc_enc;
751 cnstr_shdsc_skcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686,
752 ctx1_iv_off);
753 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
754 desc_bytes(desc), ctx->dir);
755
756 /* skcipher_decrypt shared descriptor */
757 desc = ctx->sh_desc_dec;
758 cnstr_shdsc_skcipher_decap(desc, &ctx->cdata, ivsize, is_rfc3686,
759 ctx1_iv_off);
760 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
761 desc_bytes(desc), ctx->dir);
762
763 return 0;
764 }
765
aes_skcipher_setkey(struct crypto_skcipher * skcipher,const u8 * key,unsigned int keylen)766 static int aes_skcipher_setkey(struct crypto_skcipher *skcipher,
767 const u8 *key, unsigned int keylen)
768 {
769 int err;
770
771 err = aes_check_keylen(keylen);
772 if (err)
773 return err;
774
775 return skcipher_setkey(skcipher, key, keylen, 0);
776 }
777
rfc3686_skcipher_setkey(struct crypto_skcipher * skcipher,const u8 * key,unsigned int keylen)778 static int rfc3686_skcipher_setkey(struct crypto_skcipher *skcipher,
779 const u8 *key, unsigned int keylen)
780 {
781 u32 ctx1_iv_off;
782 int err;
783
784 /*
785 * RFC3686 specific:
786 * | CONTEXT1[255:128] = {NONCE, IV, COUNTER}
787 * | *key = {KEY, NONCE}
788 */
789 ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
790 keylen -= CTR_RFC3686_NONCE_SIZE;
791
792 err = aes_check_keylen(keylen);
793 if (err)
794 return err;
795
796 return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
797 }
798
ctr_skcipher_setkey(struct crypto_skcipher * skcipher,const u8 * key,unsigned int keylen)799 static int ctr_skcipher_setkey(struct crypto_skcipher *skcipher,
800 const u8 *key, unsigned int keylen)
801 {
802 u32 ctx1_iv_off;
803 int err;
804
805 /*
806 * AES-CTR needs to load IV in CONTEXT1 reg
807 * at an offset of 128bits (16bytes)
808 * CONTEXT1[255:128] = IV
809 */
810 ctx1_iv_off = 16;
811
812 err = aes_check_keylen(keylen);
813 if (err)
814 return err;
815
816 return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
817 }
818
des_skcipher_setkey(struct crypto_skcipher * skcipher,const u8 * key,unsigned int keylen)819 static int des_skcipher_setkey(struct crypto_skcipher *skcipher,
820 const u8 *key, unsigned int keylen)
821 {
822 return verify_skcipher_des_key(skcipher, key) ?:
823 skcipher_setkey(skcipher, key, keylen, 0);
824 }
825
des3_skcipher_setkey(struct crypto_skcipher * skcipher,const u8 * key,unsigned int keylen)826 static int des3_skcipher_setkey(struct crypto_skcipher *skcipher,
827 const u8 *key, unsigned int keylen)
828 {
829 return verify_skcipher_des3_key(skcipher, key) ?:
830 skcipher_setkey(skcipher, key, keylen, 0);
831 }
832
xts_skcipher_setkey(struct crypto_skcipher * skcipher,const u8 * key,unsigned int keylen)833 static int xts_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
834 unsigned int keylen)
835 {
836 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
837 struct device *jrdev = ctx->jrdev;
838 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
839 u32 *desc;
840 int err;
841
842 err = xts_verify_key(skcipher, key, keylen);
843 if (err) {
844 dev_dbg(jrdev, "key size mismatch\n");
845 return err;
846 }
847
848 if (keylen != 2 * AES_KEYSIZE_128 && keylen != 2 * AES_KEYSIZE_256)
849 ctx->xts_key_fallback = true;
850
851 if (ctrlpriv->era <= 8 || ctx->xts_key_fallback) {
852 err = crypto_skcipher_setkey(ctx->fallback, key, keylen);
853 if (err)
854 return err;
855 }
856
857 ctx->cdata.keylen = keylen;
858 ctx->cdata.key_virt = key;
859 ctx->cdata.key_inline = true;
860
861 /* xts_skcipher_encrypt shared descriptor */
862 desc = ctx->sh_desc_enc;
863 cnstr_shdsc_xts_skcipher_encap(desc, &ctx->cdata);
864 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
865 desc_bytes(desc), ctx->dir);
866
867 /* xts_skcipher_decrypt shared descriptor */
868 desc = ctx->sh_desc_dec;
869 cnstr_shdsc_xts_skcipher_decap(desc, &ctx->cdata);
870 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
871 desc_bytes(desc), ctx->dir);
872
873 return 0;
874 }
875
876 /*
877 * aead_edesc - s/w-extended aead descriptor
878 * @src_nents: number of segments in input s/w scatterlist
879 * @dst_nents: number of segments in output s/w scatterlist
880 * @mapped_src_nents: number of segments in input h/w link table
881 * @mapped_dst_nents: number of segments in output h/w link table
882 * @sec4_sg_bytes: length of dma mapped sec4_sg space
883 * @bklog: stored to determine if the request needs backlog
884 * @sec4_sg_dma: bus physical mapped address of h/w link table
885 * @sec4_sg: pointer to h/w link table
886 * @hw_desc: the h/w job descriptor followed by any referenced link tables
887 */
888 struct aead_edesc {
889 int src_nents;
890 int dst_nents;
891 int mapped_src_nents;
892 int mapped_dst_nents;
893 int sec4_sg_bytes;
894 bool bklog;
895 dma_addr_t sec4_sg_dma;
896 struct sec4_sg_entry *sec4_sg;
897 u32 hw_desc[];
898 };
899
900 /*
901 * skcipher_edesc - s/w-extended skcipher descriptor
902 * @src_nents: number of segments in input s/w scatterlist
903 * @dst_nents: number of segments in output s/w scatterlist
904 * @mapped_src_nents: number of segments in input h/w link table
905 * @mapped_dst_nents: number of segments in output h/w link table
906 * @iv_dma: dma address of iv for checking continuity and link table
907 * @sec4_sg_bytes: length of dma mapped sec4_sg space
908 * @bklog: stored to determine if the request needs backlog
909 * @sec4_sg_dma: bus physical mapped address of h/w link table
910 * @sec4_sg: pointer to h/w link table
911 * @hw_desc: the h/w job descriptor followed by any referenced link tables
912 * and IV
913 */
914 struct skcipher_edesc {
915 int src_nents;
916 int dst_nents;
917 int mapped_src_nents;
918 int mapped_dst_nents;
919 dma_addr_t iv_dma;
920 int sec4_sg_bytes;
921 bool bklog;
922 dma_addr_t sec4_sg_dma;
923 struct sec4_sg_entry *sec4_sg;
924 u32 hw_desc[];
925 };
926
caam_unmap(struct device * dev,struct scatterlist * src,struct scatterlist * dst,int src_nents,int dst_nents,dma_addr_t iv_dma,int ivsize,dma_addr_t sec4_sg_dma,int sec4_sg_bytes)927 static void caam_unmap(struct device *dev, struct scatterlist *src,
928 struct scatterlist *dst, int src_nents,
929 int dst_nents,
930 dma_addr_t iv_dma, int ivsize, dma_addr_t sec4_sg_dma,
931 int sec4_sg_bytes)
932 {
933 if (dst != src) {
934 if (src_nents)
935 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
936 if (dst_nents)
937 dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
938 } else {
939 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
940 }
941
942 if (iv_dma)
943 dma_unmap_single(dev, iv_dma, ivsize, DMA_BIDIRECTIONAL);
944 if (sec4_sg_bytes)
945 dma_unmap_single(dev, sec4_sg_dma, sec4_sg_bytes,
946 DMA_TO_DEVICE);
947 }
948
aead_unmap(struct device * dev,struct aead_edesc * edesc,struct aead_request * req)949 static void aead_unmap(struct device *dev,
950 struct aead_edesc *edesc,
951 struct aead_request *req)
952 {
953 caam_unmap(dev, req->src, req->dst,
954 edesc->src_nents, edesc->dst_nents, 0, 0,
955 edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
956 }
957
skcipher_unmap(struct device * dev,struct skcipher_edesc * edesc,struct skcipher_request * req)958 static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc,
959 struct skcipher_request *req)
960 {
961 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
962 int ivsize = crypto_skcipher_ivsize(skcipher);
963
964 caam_unmap(dev, req->src, req->dst,
965 edesc->src_nents, edesc->dst_nents,
966 edesc->iv_dma, ivsize,
967 edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
968 }
969
aead_crypt_done(struct device * jrdev,u32 * desc,u32 err,void * context)970 static void aead_crypt_done(struct device *jrdev, u32 *desc, u32 err,
971 void *context)
972 {
973 struct aead_request *req = context;
974 struct caam_aead_req_ctx *rctx = aead_request_ctx(req);
975 struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev);
976 struct aead_edesc *edesc;
977 int ecode = 0;
978 bool has_bklog;
979
980 dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
981
982 edesc = rctx->edesc;
983 has_bklog = edesc->bklog;
984
985 if (err)
986 ecode = caam_jr_strstatus(jrdev, err);
987
988 aead_unmap(jrdev, edesc, req);
989
990 kfree(edesc);
991
992 /*
993 * If no backlog flag, the completion of the request is done
994 * by CAAM, not crypto engine.
995 */
996 if (!has_bklog)
997 aead_request_complete(req, ecode);
998 else
999 crypto_finalize_aead_request(jrp->engine, req, ecode);
1000 }
1001
skcipher_crypt_done(struct device * jrdev,u32 * desc,u32 err,void * context)1002 static void skcipher_crypt_done(struct device *jrdev, u32 *desc, u32 err,
1003 void *context)
1004 {
1005 struct skcipher_request *req = context;
1006 struct skcipher_edesc *edesc;
1007 struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req);
1008 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1009 struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev);
1010 int ivsize = crypto_skcipher_ivsize(skcipher);
1011 int ecode = 0;
1012 bool has_bklog;
1013
1014 dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
1015
1016 edesc = rctx->edesc;
1017 has_bklog = edesc->bklog;
1018 if (err)
1019 ecode = caam_jr_strstatus(jrdev, err);
1020
1021 skcipher_unmap(jrdev, edesc, req);
1022
1023 /*
1024 * The crypto API expects us to set the IV (req->iv) to the last
1025 * ciphertext block (CBC mode) or last counter (CTR mode).
1026 * This is used e.g. by the CTS mode.
1027 */
1028 if (ivsize && !ecode) {
1029 memcpy(req->iv, (u8 *)edesc->sec4_sg + edesc->sec4_sg_bytes,
1030 ivsize);
1031
1032 print_hex_dump_debug("dstiv @" __stringify(__LINE__)": ",
1033 DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
1034 ivsize, 1);
1035 }
1036
1037 caam_dump_sg("dst @" __stringify(__LINE__)": ",
1038 DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
1039 edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
1040
1041 kfree(edesc);
1042
1043 /*
1044 * If no backlog flag, the completion of the request is done
1045 * by CAAM, not crypto engine.
1046 */
1047 if (!has_bklog)
1048 skcipher_request_complete(req, ecode);
1049 else
1050 crypto_finalize_skcipher_request(jrp->engine, req, ecode);
1051 }
1052
1053 /*
1054 * Fill in aead job descriptor
1055 */
init_aead_job(struct aead_request * req,struct aead_edesc * edesc,bool all_contig,bool encrypt)1056 static void init_aead_job(struct aead_request *req,
1057 struct aead_edesc *edesc,
1058 bool all_contig, bool encrypt)
1059 {
1060 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1061 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1062 int authsize = ctx->authsize;
1063 u32 *desc = edesc->hw_desc;
1064 u32 out_options, in_options;
1065 dma_addr_t dst_dma, src_dma;
1066 int len, sec4_sg_index = 0;
1067 dma_addr_t ptr;
1068 u32 *sh_desc;
1069
1070 sh_desc = encrypt ? ctx->sh_desc_enc : ctx->sh_desc_dec;
1071 ptr = encrypt ? ctx->sh_desc_enc_dma : ctx->sh_desc_dec_dma;
1072
1073 len = desc_len(sh_desc);
1074 init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
1075
1076 if (all_contig) {
1077 src_dma = edesc->mapped_src_nents ? sg_dma_address(req->src) :
1078 0;
1079 in_options = 0;
1080 } else {
1081 src_dma = edesc->sec4_sg_dma;
1082 sec4_sg_index += edesc->mapped_src_nents;
1083 in_options = LDST_SGF;
1084 }
1085
1086 append_seq_in_ptr(desc, src_dma, req->assoclen + req->cryptlen,
1087 in_options);
1088
1089 dst_dma = src_dma;
1090 out_options = in_options;
1091
1092 if (unlikely(req->src != req->dst)) {
1093 if (!edesc->mapped_dst_nents) {
1094 dst_dma = 0;
1095 out_options = 0;
1096 } else if (edesc->mapped_dst_nents == 1) {
1097 dst_dma = sg_dma_address(req->dst);
1098 out_options = 0;
1099 } else {
1100 dst_dma = edesc->sec4_sg_dma +
1101 sec4_sg_index *
1102 sizeof(struct sec4_sg_entry);
1103 out_options = LDST_SGF;
1104 }
1105 }
1106
1107 if (encrypt)
1108 append_seq_out_ptr(desc, dst_dma,
1109 req->assoclen + req->cryptlen + authsize,
1110 out_options);
1111 else
1112 append_seq_out_ptr(desc, dst_dma,
1113 req->assoclen + req->cryptlen - authsize,
1114 out_options);
1115 }
1116
init_gcm_job(struct aead_request * req,struct aead_edesc * edesc,bool all_contig,bool encrypt)1117 static void init_gcm_job(struct aead_request *req,
1118 struct aead_edesc *edesc,
1119 bool all_contig, bool encrypt)
1120 {
1121 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1122 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1123 unsigned int ivsize = crypto_aead_ivsize(aead);
1124 u32 *desc = edesc->hw_desc;
1125 bool generic_gcm = (ivsize == GCM_AES_IV_SIZE);
1126 unsigned int last;
1127
1128 init_aead_job(req, edesc, all_contig, encrypt);
1129 append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
1130
1131 /* BUG This should not be specific to generic GCM. */
1132 last = 0;
1133 if (encrypt && generic_gcm && !(req->assoclen + req->cryptlen))
1134 last = FIFOLD_TYPE_LAST1;
1135
1136 /* Read GCM IV */
1137 append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
1138 FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | GCM_AES_IV_SIZE | last);
1139 /* Append Salt */
1140 if (!generic_gcm)
1141 append_data(desc, ctx->key + ctx->cdata.keylen, 4);
1142 /* Append IV */
1143 append_data(desc, req->iv, ivsize);
1144 /* End of blank commands */
1145 }
1146
init_chachapoly_job(struct aead_request * req,struct aead_edesc * edesc,bool all_contig,bool encrypt)1147 static void init_chachapoly_job(struct aead_request *req,
1148 struct aead_edesc *edesc, bool all_contig,
1149 bool encrypt)
1150 {
1151 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1152 unsigned int ivsize = crypto_aead_ivsize(aead);
1153 unsigned int assoclen = req->assoclen;
1154 u32 *desc = edesc->hw_desc;
1155 u32 ctx_iv_off = 4;
1156
1157 init_aead_job(req, edesc, all_contig, encrypt);
1158
1159 if (ivsize != CHACHAPOLY_IV_SIZE) {
1160 /* IPsec specific: CONTEXT1[223:128] = {NONCE, IV} */
1161 ctx_iv_off += 4;
1162
1163 /*
1164 * The associated data comes already with the IV but we need
1165 * to skip it when we authenticate or encrypt...
1166 */
1167 assoclen -= ivsize;
1168 }
1169
1170 append_math_add_imm_u32(desc, REG3, ZERO, IMM, assoclen);
1171
1172 /*
1173 * For IPsec load the IV further in the same register.
1174 * For RFC7539 simply load the 12 bytes nonce in a single operation
1175 */
1176 append_load_as_imm(desc, req->iv, ivsize, LDST_CLASS_1_CCB |
1177 LDST_SRCDST_BYTE_CONTEXT |
1178 ctx_iv_off << LDST_OFFSET_SHIFT);
1179 }
1180
init_authenc_job(struct aead_request * req,struct aead_edesc * edesc,bool all_contig,bool encrypt)1181 static void init_authenc_job(struct aead_request *req,
1182 struct aead_edesc *edesc,
1183 bool all_contig, bool encrypt)
1184 {
1185 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1186 struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
1187 struct caam_aead_alg, aead);
1188 unsigned int ivsize = crypto_aead_ivsize(aead);
1189 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1190 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
1191 const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
1192 OP_ALG_AAI_CTR_MOD128);
1193 const bool is_rfc3686 = alg->caam.rfc3686;
1194 u32 *desc = edesc->hw_desc;
1195 u32 ivoffset = 0;
1196
1197 /*
1198 * AES-CTR needs to load IV in CONTEXT1 reg
1199 * at an offset of 128bits (16bytes)
1200 * CONTEXT1[255:128] = IV
1201 */
1202 if (ctr_mode)
1203 ivoffset = 16;
1204
1205 /*
1206 * RFC3686 specific:
1207 * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
1208 */
1209 if (is_rfc3686)
1210 ivoffset = 16 + CTR_RFC3686_NONCE_SIZE;
1211
1212 init_aead_job(req, edesc, all_contig, encrypt);
1213
1214 /*
1215 * {REG3, DPOVRD} = assoclen, depending on whether MATH command supports
1216 * having DPOVRD as destination.
1217 */
1218 if (ctrlpriv->era < 3)
1219 append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
1220 else
1221 append_math_add_imm_u32(desc, DPOVRD, ZERO, IMM, req->assoclen);
1222
1223 if (ivsize && ((is_rfc3686 && encrypt) || !alg->caam.geniv))
1224 append_load_as_imm(desc, req->iv, ivsize,
1225 LDST_CLASS_1_CCB |
1226 LDST_SRCDST_BYTE_CONTEXT |
1227 (ivoffset << LDST_OFFSET_SHIFT));
1228 }
1229
1230 /*
1231 * Fill in skcipher job descriptor
1232 */
init_skcipher_job(struct skcipher_request * req,struct skcipher_edesc * edesc,const bool encrypt)1233 static void init_skcipher_job(struct skcipher_request *req,
1234 struct skcipher_edesc *edesc,
1235 const bool encrypt)
1236 {
1237 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1238 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
1239 struct device *jrdev = ctx->jrdev;
1240 int ivsize = crypto_skcipher_ivsize(skcipher);
1241 u32 *desc = edesc->hw_desc;
1242 u32 *sh_desc;
1243 u32 in_options = 0, out_options = 0;
1244 dma_addr_t src_dma, dst_dma, ptr;
1245 int len, sec4_sg_index = 0;
1246
1247 print_hex_dump_debug("presciv@"__stringify(__LINE__)": ",
1248 DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1);
1249 dev_dbg(jrdev, "asked=%d, cryptlen%d\n",
1250 (int)edesc->src_nents > 1 ? 100 : req->cryptlen, req->cryptlen);
1251
1252 caam_dump_sg("src @" __stringify(__LINE__)": ",
1253 DUMP_PREFIX_ADDRESS, 16, 4, req->src,
1254 edesc->src_nents > 1 ? 100 : req->cryptlen, 1);
1255
1256 sh_desc = encrypt ? ctx->sh_desc_enc : ctx->sh_desc_dec;
1257 ptr = encrypt ? ctx->sh_desc_enc_dma : ctx->sh_desc_dec_dma;
1258
1259 len = desc_len(sh_desc);
1260 init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
1261
1262 if (ivsize || edesc->mapped_src_nents > 1) {
1263 src_dma = edesc->sec4_sg_dma;
1264 sec4_sg_index = edesc->mapped_src_nents + !!ivsize;
1265 in_options = LDST_SGF;
1266 } else {
1267 src_dma = sg_dma_address(req->src);
1268 }
1269
1270 append_seq_in_ptr(desc, src_dma, req->cryptlen + ivsize, in_options);
1271
1272 if (likely(req->src == req->dst)) {
1273 dst_dma = src_dma + !!ivsize * sizeof(struct sec4_sg_entry);
1274 out_options = in_options;
1275 } else if (!ivsize && edesc->mapped_dst_nents == 1) {
1276 dst_dma = sg_dma_address(req->dst);
1277 } else {
1278 dst_dma = edesc->sec4_sg_dma + sec4_sg_index *
1279 sizeof(struct sec4_sg_entry);
1280 out_options = LDST_SGF;
1281 }
1282
1283 append_seq_out_ptr(desc, dst_dma, req->cryptlen + ivsize, out_options);
1284 }
1285
1286 /*
1287 * allocate and map the aead extended descriptor
1288 */
aead_edesc_alloc(struct aead_request * req,int desc_bytes,bool * all_contig_ptr,bool encrypt)1289 static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
1290 int desc_bytes, bool *all_contig_ptr,
1291 bool encrypt)
1292 {
1293 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1294 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1295 struct device *jrdev = ctx->jrdev;
1296 struct caam_aead_req_ctx *rctx = aead_request_ctx(req);
1297 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
1298 GFP_KERNEL : GFP_ATOMIC;
1299 int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
1300 int src_len, dst_len = 0;
1301 struct aead_edesc *edesc;
1302 int sec4_sg_index, sec4_sg_len, sec4_sg_bytes;
1303 unsigned int authsize = ctx->authsize;
1304
1305 if (unlikely(req->dst != req->src)) {
1306 src_len = req->assoclen + req->cryptlen;
1307 dst_len = src_len + (encrypt ? authsize : (-authsize));
1308
1309 src_nents = sg_nents_for_len(req->src, src_len);
1310 if (unlikely(src_nents < 0)) {
1311 dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
1312 src_len);
1313 return ERR_PTR(src_nents);
1314 }
1315
1316 dst_nents = sg_nents_for_len(req->dst, dst_len);
1317 if (unlikely(dst_nents < 0)) {
1318 dev_err(jrdev, "Insufficient bytes (%d) in dst S/G\n",
1319 dst_len);
1320 return ERR_PTR(dst_nents);
1321 }
1322 } else {
1323 src_len = req->assoclen + req->cryptlen +
1324 (encrypt ? authsize : 0);
1325
1326 src_nents = sg_nents_for_len(req->src, src_len);
1327 if (unlikely(src_nents < 0)) {
1328 dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
1329 src_len);
1330 return ERR_PTR(src_nents);
1331 }
1332 }
1333
1334 if (likely(req->src == req->dst)) {
1335 mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
1336 DMA_BIDIRECTIONAL);
1337 if (unlikely(!mapped_src_nents)) {
1338 dev_err(jrdev, "unable to map source\n");
1339 return ERR_PTR(-ENOMEM);
1340 }
1341 } else {
1342 /* Cover also the case of null (zero length) input data */
1343 if (src_nents) {
1344 mapped_src_nents = dma_map_sg(jrdev, req->src,
1345 src_nents, DMA_TO_DEVICE);
1346 if (unlikely(!mapped_src_nents)) {
1347 dev_err(jrdev, "unable to map source\n");
1348 return ERR_PTR(-ENOMEM);
1349 }
1350 } else {
1351 mapped_src_nents = 0;
1352 }
1353
1354 /* Cover also the case of null (zero length) output data */
1355 if (dst_nents) {
1356 mapped_dst_nents = dma_map_sg(jrdev, req->dst,
1357 dst_nents,
1358 DMA_FROM_DEVICE);
1359 if (unlikely(!mapped_dst_nents)) {
1360 dev_err(jrdev, "unable to map destination\n");
1361 dma_unmap_sg(jrdev, req->src, src_nents,
1362 DMA_TO_DEVICE);
1363 return ERR_PTR(-ENOMEM);
1364 }
1365 } else {
1366 mapped_dst_nents = 0;
1367 }
1368 }
1369
1370 /*
1371 * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
1372 * the end of the table by allocating more S/G entries.
1373 */
1374 sec4_sg_len = mapped_src_nents > 1 ? mapped_src_nents : 0;
1375 if (mapped_dst_nents > 1)
1376 sec4_sg_len += pad_sg_nents(mapped_dst_nents);
1377 else
1378 sec4_sg_len = pad_sg_nents(sec4_sg_len);
1379
1380 sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
1381
1382 /* allocate space for base edesc and hw desc commands, link tables */
1383 edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
1384 GFP_DMA | flags);
1385 if (!edesc) {
1386 caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
1387 0, 0, 0);
1388 return ERR_PTR(-ENOMEM);
1389 }
1390
1391 edesc->src_nents = src_nents;
1392 edesc->dst_nents = dst_nents;
1393 edesc->mapped_src_nents = mapped_src_nents;
1394 edesc->mapped_dst_nents = mapped_dst_nents;
1395 edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
1396 desc_bytes;
1397
1398 rctx->edesc = edesc;
1399
1400 *all_contig_ptr = !(mapped_src_nents > 1);
1401
1402 sec4_sg_index = 0;
1403 if (mapped_src_nents > 1) {
1404 sg_to_sec4_sg_last(req->src, src_len,
1405 edesc->sec4_sg + sec4_sg_index, 0);
1406 sec4_sg_index += mapped_src_nents;
1407 }
1408 if (mapped_dst_nents > 1) {
1409 sg_to_sec4_sg_last(req->dst, dst_len,
1410 edesc->sec4_sg + sec4_sg_index, 0);
1411 }
1412
1413 if (!sec4_sg_bytes)
1414 return edesc;
1415
1416 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1417 sec4_sg_bytes, DMA_TO_DEVICE);
1418 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1419 dev_err(jrdev, "unable to map S/G table\n");
1420 aead_unmap(jrdev, edesc, req);
1421 kfree(edesc);
1422 return ERR_PTR(-ENOMEM);
1423 }
1424
1425 edesc->sec4_sg_bytes = sec4_sg_bytes;
1426
1427 return edesc;
1428 }
1429
aead_enqueue_req(struct device * jrdev,struct aead_request * req)1430 static int aead_enqueue_req(struct device *jrdev, struct aead_request *req)
1431 {
1432 struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev);
1433 struct caam_aead_req_ctx *rctx = aead_request_ctx(req);
1434 struct aead_edesc *edesc = rctx->edesc;
1435 u32 *desc = edesc->hw_desc;
1436 int ret;
1437
1438 /*
1439 * Only the backlog request are sent to crypto-engine since the others
1440 * can be handled by CAAM, if free, especially since JR has up to 1024
1441 * entries (more than the 10 entries from crypto-engine).
1442 */
1443 if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)
1444 ret = crypto_transfer_aead_request_to_engine(jrpriv->engine,
1445 req);
1446 else
1447 ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req);
1448
1449 if ((ret != -EINPROGRESS) && (ret != -EBUSY)) {
1450 aead_unmap(jrdev, edesc, req);
1451 kfree(rctx->edesc);
1452 }
1453
1454 return ret;
1455 }
1456
chachapoly_crypt(struct aead_request * req,bool encrypt)1457 static inline int chachapoly_crypt(struct aead_request *req, bool encrypt)
1458 {
1459 struct aead_edesc *edesc;
1460 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1461 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1462 struct device *jrdev = ctx->jrdev;
1463 bool all_contig;
1464 u32 *desc;
1465
1466 edesc = aead_edesc_alloc(req, CHACHAPOLY_DESC_JOB_IO_LEN, &all_contig,
1467 encrypt);
1468 if (IS_ERR(edesc))
1469 return PTR_ERR(edesc);
1470
1471 desc = edesc->hw_desc;
1472
1473 init_chachapoly_job(req, edesc, all_contig, encrypt);
1474 print_hex_dump_debug("chachapoly jobdesc@" __stringify(__LINE__)": ",
1475 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
1476 1);
1477
1478 return aead_enqueue_req(jrdev, req);
1479 }
1480
chachapoly_encrypt(struct aead_request * req)1481 static int chachapoly_encrypt(struct aead_request *req)
1482 {
1483 return chachapoly_crypt(req, true);
1484 }
1485
chachapoly_decrypt(struct aead_request * req)1486 static int chachapoly_decrypt(struct aead_request *req)
1487 {
1488 return chachapoly_crypt(req, false);
1489 }
1490
aead_crypt(struct aead_request * req,bool encrypt)1491 static inline int aead_crypt(struct aead_request *req, bool encrypt)
1492 {
1493 struct aead_edesc *edesc;
1494 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1495 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1496 struct device *jrdev = ctx->jrdev;
1497 bool all_contig;
1498
1499 /* allocate extended descriptor */
1500 edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN,
1501 &all_contig, encrypt);
1502 if (IS_ERR(edesc))
1503 return PTR_ERR(edesc);
1504
1505 /* Create and submit job descriptor */
1506 init_authenc_job(req, edesc, all_contig, encrypt);
1507
1508 print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ",
1509 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1510 desc_bytes(edesc->hw_desc), 1);
1511
1512 return aead_enqueue_req(jrdev, req);
1513 }
1514
aead_encrypt(struct aead_request * req)1515 static int aead_encrypt(struct aead_request *req)
1516 {
1517 return aead_crypt(req, true);
1518 }
1519
aead_decrypt(struct aead_request * req)1520 static int aead_decrypt(struct aead_request *req)
1521 {
1522 return aead_crypt(req, false);
1523 }
1524
aead_do_one_req(struct crypto_engine * engine,void * areq)1525 static int aead_do_one_req(struct crypto_engine *engine, void *areq)
1526 {
1527 struct aead_request *req = aead_request_cast(areq);
1528 struct caam_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1529 struct caam_aead_req_ctx *rctx = aead_request_ctx(req);
1530 u32 *desc = rctx->edesc->hw_desc;
1531 int ret;
1532
1533 rctx->edesc->bklog = true;
1534
1535 ret = caam_jr_enqueue(ctx->jrdev, desc, aead_crypt_done, req);
1536
1537 if (ret == -ENOSPC && engine->retry_support)
1538 return ret;
1539
1540 if (ret != -EINPROGRESS) {
1541 aead_unmap(ctx->jrdev, rctx->edesc, req);
1542 kfree(rctx->edesc);
1543 } else {
1544 ret = 0;
1545 }
1546
1547 return ret;
1548 }
1549
gcm_crypt(struct aead_request * req,bool encrypt)1550 static inline int gcm_crypt(struct aead_request *req, bool encrypt)
1551 {
1552 struct aead_edesc *edesc;
1553 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1554 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1555 struct device *jrdev = ctx->jrdev;
1556 bool all_contig;
1557
1558 /* allocate extended descriptor */
1559 edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig,
1560 encrypt);
1561 if (IS_ERR(edesc))
1562 return PTR_ERR(edesc);
1563
1564 /* Create and submit job descriptor */
1565 init_gcm_job(req, edesc, all_contig, encrypt);
1566
1567 print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ",
1568 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1569 desc_bytes(edesc->hw_desc), 1);
1570
1571 return aead_enqueue_req(jrdev, req);
1572 }
1573
gcm_encrypt(struct aead_request * req)1574 static int gcm_encrypt(struct aead_request *req)
1575 {
1576 return gcm_crypt(req, true);
1577 }
1578
gcm_decrypt(struct aead_request * req)1579 static int gcm_decrypt(struct aead_request *req)
1580 {
1581 return gcm_crypt(req, false);
1582 }
1583
ipsec_gcm_encrypt(struct aead_request * req)1584 static int ipsec_gcm_encrypt(struct aead_request *req)
1585 {
1586 return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_encrypt(req);
1587 }
1588
ipsec_gcm_decrypt(struct aead_request * req)1589 static int ipsec_gcm_decrypt(struct aead_request *req)
1590 {
1591 return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_decrypt(req);
1592 }
1593
1594 /*
1595 * allocate and map the skcipher extended descriptor for skcipher
1596 */
skcipher_edesc_alloc(struct skcipher_request * req,int desc_bytes)1597 static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req,
1598 int desc_bytes)
1599 {
1600 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1601 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
1602 struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req);
1603 struct device *jrdev = ctx->jrdev;
1604 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
1605 GFP_KERNEL : GFP_ATOMIC;
1606 int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
1607 struct skcipher_edesc *edesc;
1608 dma_addr_t iv_dma = 0;
1609 u8 *iv;
1610 int ivsize = crypto_skcipher_ivsize(skcipher);
1611 int dst_sg_idx, sec4_sg_ents, sec4_sg_bytes;
1612
1613 src_nents = sg_nents_for_len(req->src, req->cryptlen);
1614 if (unlikely(src_nents < 0)) {
1615 dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
1616 req->cryptlen);
1617 return ERR_PTR(src_nents);
1618 }
1619
1620 if (req->dst != req->src) {
1621 dst_nents = sg_nents_for_len(req->dst, req->cryptlen);
1622 if (unlikely(dst_nents < 0)) {
1623 dev_err(jrdev, "Insufficient bytes (%d) in dst S/G\n",
1624 req->cryptlen);
1625 return ERR_PTR(dst_nents);
1626 }
1627 }
1628
1629 if (likely(req->src == req->dst)) {
1630 mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
1631 DMA_BIDIRECTIONAL);
1632 if (unlikely(!mapped_src_nents)) {
1633 dev_err(jrdev, "unable to map source\n");
1634 return ERR_PTR(-ENOMEM);
1635 }
1636 } else {
1637 mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
1638 DMA_TO_DEVICE);
1639 if (unlikely(!mapped_src_nents)) {
1640 dev_err(jrdev, "unable to map source\n");
1641 return ERR_PTR(-ENOMEM);
1642 }
1643 mapped_dst_nents = dma_map_sg(jrdev, req->dst, dst_nents,
1644 DMA_FROM_DEVICE);
1645 if (unlikely(!mapped_dst_nents)) {
1646 dev_err(jrdev, "unable to map destination\n");
1647 dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
1648 return ERR_PTR(-ENOMEM);
1649 }
1650 }
1651
1652 if (!ivsize && mapped_src_nents == 1)
1653 sec4_sg_ents = 0; // no need for an input hw s/g table
1654 else
1655 sec4_sg_ents = mapped_src_nents + !!ivsize;
1656 dst_sg_idx = sec4_sg_ents;
1657
1658 /*
1659 * Input, output HW S/G tables: [IV, src][dst, IV]
1660 * IV entries point to the same buffer
1661 * If src == dst, S/G entries are reused (S/G tables overlap)
1662 *
1663 * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
1664 * the end of the table by allocating more S/G entries. Logic:
1665 * if (output S/G)
1666 * pad output S/G, if needed
1667 * else if (input S/G) ...
1668 * pad input S/G, if needed
1669 */
1670 if (ivsize || mapped_dst_nents > 1) {
1671 if (req->src == req->dst)
1672 sec4_sg_ents = !!ivsize + pad_sg_nents(sec4_sg_ents);
1673 else
1674 sec4_sg_ents += pad_sg_nents(mapped_dst_nents +
1675 !!ivsize);
1676 } else {
1677 sec4_sg_ents = pad_sg_nents(sec4_sg_ents);
1678 }
1679
1680 sec4_sg_bytes = sec4_sg_ents * sizeof(struct sec4_sg_entry);
1681
1682 /*
1683 * allocate space for base edesc and hw desc commands, link tables, IV
1684 */
1685 edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes + ivsize,
1686 GFP_DMA | flags);
1687 if (!edesc) {
1688 dev_err(jrdev, "could not allocate extended descriptor\n");
1689 caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
1690 0, 0, 0);
1691 return ERR_PTR(-ENOMEM);
1692 }
1693
1694 edesc->src_nents = src_nents;
1695 edesc->dst_nents = dst_nents;
1696 edesc->mapped_src_nents = mapped_src_nents;
1697 edesc->mapped_dst_nents = mapped_dst_nents;
1698 edesc->sec4_sg_bytes = sec4_sg_bytes;
1699 edesc->sec4_sg = (struct sec4_sg_entry *)((u8 *)edesc->hw_desc +
1700 desc_bytes);
1701 rctx->edesc = edesc;
1702
1703 /* Make sure IV is located in a DMAable area */
1704 if (ivsize) {
1705 iv = (u8 *)edesc->sec4_sg + sec4_sg_bytes;
1706 memcpy(iv, req->iv, ivsize);
1707
1708 iv_dma = dma_map_single(jrdev, iv, ivsize, DMA_BIDIRECTIONAL);
1709 if (dma_mapping_error(jrdev, iv_dma)) {
1710 dev_err(jrdev, "unable to map IV\n");
1711 caam_unmap(jrdev, req->src, req->dst, src_nents,
1712 dst_nents, 0, 0, 0, 0);
1713 kfree(edesc);
1714 return ERR_PTR(-ENOMEM);
1715 }
1716
1717 dma_to_sec4_sg_one(edesc->sec4_sg, iv_dma, ivsize, 0);
1718 }
1719 if (dst_sg_idx)
1720 sg_to_sec4_sg(req->src, req->cryptlen, edesc->sec4_sg +
1721 !!ivsize, 0);
1722
1723 if (req->src != req->dst && (ivsize || mapped_dst_nents > 1))
1724 sg_to_sec4_sg(req->dst, req->cryptlen, edesc->sec4_sg +
1725 dst_sg_idx, 0);
1726
1727 if (ivsize)
1728 dma_to_sec4_sg_one(edesc->sec4_sg + dst_sg_idx +
1729 mapped_dst_nents, iv_dma, ivsize, 0);
1730
1731 if (ivsize || mapped_dst_nents > 1)
1732 sg_to_sec4_set_last(edesc->sec4_sg + dst_sg_idx +
1733 mapped_dst_nents - 1 + !!ivsize);
1734
1735 if (sec4_sg_bytes) {
1736 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1737 sec4_sg_bytes,
1738 DMA_TO_DEVICE);
1739 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1740 dev_err(jrdev, "unable to map S/G table\n");
1741 caam_unmap(jrdev, req->src, req->dst, src_nents,
1742 dst_nents, iv_dma, ivsize, 0, 0);
1743 kfree(edesc);
1744 return ERR_PTR(-ENOMEM);
1745 }
1746 }
1747
1748 edesc->iv_dma = iv_dma;
1749
1750 print_hex_dump_debug("skcipher sec4_sg@" __stringify(__LINE__)": ",
1751 DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
1752 sec4_sg_bytes, 1);
1753
1754 return edesc;
1755 }
1756
skcipher_do_one_req(struct crypto_engine * engine,void * areq)1757 static int skcipher_do_one_req(struct crypto_engine *engine, void *areq)
1758 {
1759 struct skcipher_request *req = skcipher_request_cast(areq);
1760 struct caam_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
1761 struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req);
1762 u32 *desc = rctx->edesc->hw_desc;
1763 int ret;
1764
1765 rctx->edesc->bklog = true;
1766
1767 ret = caam_jr_enqueue(ctx->jrdev, desc, skcipher_crypt_done, req);
1768
1769 if (ret == -ENOSPC && engine->retry_support)
1770 return ret;
1771
1772 if (ret != -EINPROGRESS) {
1773 skcipher_unmap(ctx->jrdev, rctx->edesc, req);
1774 kfree(rctx->edesc);
1775 } else {
1776 ret = 0;
1777 }
1778
1779 return ret;
1780 }
1781
xts_skcipher_ivsize(struct skcipher_request * req)1782 static inline bool xts_skcipher_ivsize(struct skcipher_request *req)
1783 {
1784 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1785 unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
1786
1787 return !!get_unaligned((u64 *)(req->iv + (ivsize / 2)));
1788 }
1789
skcipher_crypt(struct skcipher_request * req,bool encrypt)1790 static inline int skcipher_crypt(struct skcipher_request *req, bool encrypt)
1791 {
1792 struct skcipher_edesc *edesc;
1793 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1794 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
1795 struct device *jrdev = ctx->jrdev;
1796 struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev);
1797 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
1798 u32 *desc;
1799 int ret = 0;
1800
1801 /*
1802 * XTS is expected to return an error even for input length = 0
1803 * Note that the case input length < block size will be caught during
1804 * HW offloading and return an error.
1805 */
1806 if (!req->cryptlen && !ctx->fallback)
1807 return 0;
1808
1809 if (ctx->fallback && ((ctrlpriv->era <= 8 && xts_skcipher_ivsize(req)) ||
1810 ctx->xts_key_fallback)) {
1811 struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req);
1812
1813 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
1814 skcipher_request_set_callback(&rctx->fallback_req,
1815 req->base.flags,
1816 req->base.complete,
1817 req->base.data);
1818 skcipher_request_set_crypt(&rctx->fallback_req, req->src,
1819 req->dst, req->cryptlen, req->iv);
1820
1821 return encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) :
1822 crypto_skcipher_decrypt(&rctx->fallback_req);
1823 }
1824
1825 /* allocate extended descriptor */
1826 edesc = skcipher_edesc_alloc(req, DESC_JOB_IO_LEN * CAAM_CMD_SZ);
1827 if (IS_ERR(edesc))
1828 return PTR_ERR(edesc);
1829
1830 /* Create and submit job descriptor*/
1831 init_skcipher_job(req, edesc, encrypt);
1832
1833 print_hex_dump_debug("skcipher jobdesc@" __stringify(__LINE__)": ",
1834 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1835 desc_bytes(edesc->hw_desc), 1);
1836
1837 desc = edesc->hw_desc;
1838 /*
1839 * Only the backlog request are sent to crypto-engine since the others
1840 * can be handled by CAAM, if free, especially since JR has up to 1024
1841 * entries (more than the 10 entries from crypto-engine).
1842 */
1843 if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)
1844 ret = crypto_transfer_skcipher_request_to_engine(jrpriv->engine,
1845 req);
1846 else
1847 ret = caam_jr_enqueue(jrdev, desc, skcipher_crypt_done, req);
1848
1849 if ((ret != -EINPROGRESS) && (ret != -EBUSY)) {
1850 skcipher_unmap(jrdev, edesc, req);
1851 kfree(edesc);
1852 }
1853
1854 return ret;
1855 }
1856
skcipher_encrypt(struct skcipher_request * req)1857 static int skcipher_encrypt(struct skcipher_request *req)
1858 {
1859 return skcipher_crypt(req, true);
1860 }
1861
skcipher_decrypt(struct skcipher_request * req)1862 static int skcipher_decrypt(struct skcipher_request *req)
1863 {
1864 return skcipher_crypt(req, false);
1865 }
1866
1867 static struct caam_skcipher_alg driver_algs[] = {
1868 {
1869 .skcipher = {
1870 .base = {
1871 .cra_name = "cbc(aes)",
1872 .cra_driver_name = "cbc-aes-caam",
1873 .cra_blocksize = AES_BLOCK_SIZE,
1874 },
1875 .setkey = aes_skcipher_setkey,
1876 .encrypt = skcipher_encrypt,
1877 .decrypt = skcipher_decrypt,
1878 .min_keysize = AES_MIN_KEY_SIZE,
1879 .max_keysize = AES_MAX_KEY_SIZE,
1880 .ivsize = AES_BLOCK_SIZE,
1881 },
1882 .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1883 },
1884 {
1885 .skcipher = {
1886 .base = {
1887 .cra_name = "cbc(des3_ede)",
1888 .cra_driver_name = "cbc-3des-caam",
1889 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1890 },
1891 .setkey = des3_skcipher_setkey,
1892 .encrypt = skcipher_encrypt,
1893 .decrypt = skcipher_decrypt,
1894 .min_keysize = DES3_EDE_KEY_SIZE,
1895 .max_keysize = DES3_EDE_KEY_SIZE,
1896 .ivsize = DES3_EDE_BLOCK_SIZE,
1897 },
1898 .caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1899 },
1900 {
1901 .skcipher = {
1902 .base = {
1903 .cra_name = "cbc(des)",
1904 .cra_driver_name = "cbc-des-caam",
1905 .cra_blocksize = DES_BLOCK_SIZE,
1906 },
1907 .setkey = des_skcipher_setkey,
1908 .encrypt = skcipher_encrypt,
1909 .decrypt = skcipher_decrypt,
1910 .min_keysize = DES_KEY_SIZE,
1911 .max_keysize = DES_KEY_SIZE,
1912 .ivsize = DES_BLOCK_SIZE,
1913 },
1914 .caam.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1915 },
1916 {
1917 .skcipher = {
1918 .base = {
1919 .cra_name = "ctr(aes)",
1920 .cra_driver_name = "ctr-aes-caam",
1921 .cra_blocksize = 1,
1922 },
1923 .setkey = ctr_skcipher_setkey,
1924 .encrypt = skcipher_encrypt,
1925 .decrypt = skcipher_decrypt,
1926 .min_keysize = AES_MIN_KEY_SIZE,
1927 .max_keysize = AES_MAX_KEY_SIZE,
1928 .ivsize = AES_BLOCK_SIZE,
1929 .chunksize = AES_BLOCK_SIZE,
1930 },
1931 .caam.class1_alg_type = OP_ALG_ALGSEL_AES |
1932 OP_ALG_AAI_CTR_MOD128,
1933 },
1934 {
1935 .skcipher = {
1936 .base = {
1937 .cra_name = "rfc3686(ctr(aes))",
1938 .cra_driver_name = "rfc3686-ctr-aes-caam",
1939 .cra_blocksize = 1,
1940 },
1941 .setkey = rfc3686_skcipher_setkey,
1942 .encrypt = skcipher_encrypt,
1943 .decrypt = skcipher_decrypt,
1944 .min_keysize = AES_MIN_KEY_SIZE +
1945 CTR_RFC3686_NONCE_SIZE,
1946 .max_keysize = AES_MAX_KEY_SIZE +
1947 CTR_RFC3686_NONCE_SIZE,
1948 .ivsize = CTR_RFC3686_IV_SIZE,
1949 .chunksize = AES_BLOCK_SIZE,
1950 },
1951 .caam = {
1952 .class1_alg_type = OP_ALG_ALGSEL_AES |
1953 OP_ALG_AAI_CTR_MOD128,
1954 .rfc3686 = true,
1955 },
1956 },
1957 {
1958 .skcipher = {
1959 .base = {
1960 .cra_name = "xts(aes)",
1961 .cra_driver_name = "xts-aes-caam",
1962 .cra_flags = CRYPTO_ALG_NEED_FALLBACK,
1963 .cra_blocksize = AES_BLOCK_SIZE,
1964 },
1965 .setkey = xts_skcipher_setkey,
1966 .encrypt = skcipher_encrypt,
1967 .decrypt = skcipher_decrypt,
1968 .min_keysize = 2 * AES_MIN_KEY_SIZE,
1969 .max_keysize = 2 * AES_MAX_KEY_SIZE,
1970 .ivsize = AES_BLOCK_SIZE,
1971 },
1972 .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
1973 },
1974 {
1975 .skcipher = {
1976 .base = {
1977 .cra_name = "ecb(des)",
1978 .cra_driver_name = "ecb-des-caam",
1979 .cra_blocksize = DES_BLOCK_SIZE,
1980 },
1981 .setkey = des_skcipher_setkey,
1982 .encrypt = skcipher_encrypt,
1983 .decrypt = skcipher_decrypt,
1984 .min_keysize = DES_KEY_SIZE,
1985 .max_keysize = DES_KEY_SIZE,
1986 },
1987 .caam.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_ECB,
1988 },
1989 {
1990 .skcipher = {
1991 .base = {
1992 .cra_name = "ecb(aes)",
1993 .cra_driver_name = "ecb-aes-caam",
1994 .cra_blocksize = AES_BLOCK_SIZE,
1995 },
1996 .setkey = aes_skcipher_setkey,
1997 .encrypt = skcipher_encrypt,
1998 .decrypt = skcipher_decrypt,
1999 .min_keysize = AES_MIN_KEY_SIZE,
2000 .max_keysize = AES_MAX_KEY_SIZE,
2001 },
2002 .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB,
2003 },
2004 {
2005 .skcipher = {
2006 .base = {
2007 .cra_name = "ecb(des3_ede)",
2008 .cra_driver_name = "ecb-des3-caam",
2009 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2010 },
2011 .setkey = des3_skcipher_setkey,
2012 .encrypt = skcipher_encrypt,
2013 .decrypt = skcipher_decrypt,
2014 .min_keysize = DES3_EDE_KEY_SIZE,
2015 .max_keysize = DES3_EDE_KEY_SIZE,
2016 },
2017 .caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_ECB,
2018 },
2019 };
2020
2021 static struct caam_aead_alg driver_aeads[] = {
2022 {
2023 .aead = {
2024 .base = {
2025 .cra_name = "rfc4106(gcm(aes))",
2026 .cra_driver_name = "rfc4106-gcm-aes-caam",
2027 .cra_blocksize = 1,
2028 },
2029 .setkey = rfc4106_setkey,
2030 .setauthsize = rfc4106_setauthsize,
2031 .encrypt = ipsec_gcm_encrypt,
2032 .decrypt = ipsec_gcm_decrypt,
2033 .ivsize = GCM_RFC4106_IV_SIZE,
2034 .maxauthsize = AES_BLOCK_SIZE,
2035 },
2036 .caam = {
2037 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2038 .nodkp = true,
2039 },
2040 },
2041 {
2042 .aead = {
2043 .base = {
2044 .cra_name = "rfc4543(gcm(aes))",
2045 .cra_driver_name = "rfc4543-gcm-aes-caam",
2046 .cra_blocksize = 1,
2047 },
2048 .setkey = rfc4543_setkey,
2049 .setauthsize = rfc4543_setauthsize,
2050 .encrypt = ipsec_gcm_encrypt,
2051 .decrypt = ipsec_gcm_decrypt,
2052 .ivsize = GCM_RFC4543_IV_SIZE,
2053 .maxauthsize = AES_BLOCK_SIZE,
2054 },
2055 .caam = {
2056 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2057 .nodkp = true,
2058 },
2059 },
2060 /* Galois Counter Mode */
2061 {
2062 .aead = {
2063 .base = {
2064 .cra_name = "gcm(aes)",
2065 .cra_driver_name = "gcm-aes-caam",
2066 .cra_blocksize = 1,
2067 },
2068 .setkey = gcm_setkey,
2069 .setauthsize = gcm_setauthsize,
2070 .encrypt = gcm_encrypt,
2071 .decrypt = gcm_decrypt,
2072 .ivsize = GCM_AES_IV_SIZE,
2073 .maxauthsize = AES_BLOCK_SIZE,
2074 },
2075 .caam = {
2076 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2077 .nodkp = true,
2078 },
2079 },
2080 /* single-pass ipsec_esp descriptor */
2081 {
2082 .aead = {
2083 .base = {
2084 .cra_name = "authenc(hmac(md5),"
2085 "ecb(cipher_null))",
2086 .cra_driver_name = "authenc-hmac-md5-"
2087 "ecb-cipher_null-caam",
2088 .cra_blocksize = NULL_BLOCK_SIZE,
2089 },
2090 .setkey = aead_setkey,
2091 .setauthsize = aead_setauthsize,
2092 .encrypt = aead_encrypt,
2093 .decrypt = aead_decrypt,
2094 .ivsize = NULL_IV_SIZE,
2095 .maxauthsize = MD5_DIGEST_SIZE,
2096 },
2097 .caam = {
2098 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2099 OP_ALG_AAI_HMAC_PRECOMP,
2100 },
2101 },
2102 {
2103 .aead = {
2104 .base = {
2105 .cra_name = "authenc(hmac(sha1),"
2106 "ecb(cipher_null))",
2107 .cra_driver_name = "authenc-hmac-sha1-"
2108 "ecb-cipher_null-caam",
2109 .cra_blocksize = NULL_BLOCK_SIZE,
2110 },
2111 .setkey = aead_setkey,
2112 .setauthsize = aead_setauthsize,
2113 .encrypt = aead_encrypt,
2114 .decrypt = aead_decrypt,
2115 .ivsize = NULL_IV_SIZE,
2116 .maxauthsize = SHA1_DIGEST_SIZE,
2117 },
2118 .caam = {
2119 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2120 OP_ALG_AAI_HMAC_PRECOMP,
2121 },
2122 },
2123 {
2124 .aead = {
2125 .base = {
2126 .cra_name = "authenc(hmac(sha224),"
2127 "ecb(cipher_null))",
2128 .cra_driver_name = "authenc-hmac-sha224-"
2129 "ecb-cipher_null-caam",
2130 .cra_blocksize = NULL_BLOCK_SIZE,
2131 },
2132 .setkey = aead_setkey,
2133 .setauthsize = aead_setauthsize,
2134 .encrypt = aead_encrypt,
2135 .decrypt = aead_decrypt,
2136 .ivsize = NULL_IV_SIZE,
2137 .maxauthsize = SHA224_DIGEST_SIZE,
2138 },
2139 .caam = {
2140 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2141 OP_ALG_AAI_HMAC_PRECOMP,
2142 },
2143 },
2144 {
2145 .aead = {
2146 .base = {
2147 .cra_name = "authenc(hmac(sha256),"
2148 "ecb(cipher_null))",
2149 .cra_driver_name = "authenc-hmac-sha256-"
2150 "ecb-cipher_null-caam",
2151 .cra_blocksize = NULL_BLOCK_SIZE,
2152 },
2153 .setkey = aead_setkey,
2154 .setauthsize = aead_setauthsize,
2155 .encrypt = aead_encrypt,
2156 .decrypt = aead_decrypt,
2157 .ivsize = NULL_IV_SIZE,
2158 .maxauthsize = SHA256_DIGEST_SIZE,
2159 },
2160 .caam = {
2161 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2162 OP_ALG_AAI_HMAC_PRECOMP,
2163 },
2164 },
2165 {
2166 .aead = {
2167 .base = {
2168 .cra_name = "authenc(hmac(sha384),"
2169 "ecb(cipher_null))",
2170 .cra_driver_name = "authenc-hmac-sha384-"
2171 "ecb-cipher_null-caam",
2172 .cra_blocksize = NULL_BLOCK_SIZE,
2173 },
2174 .setkey = aead_setkey,
2175 .setauthsize = aead_setauthsize,
2176 .encrypt = aead_encrypt,
2177 .decrypt = aead_decrypt,
2178 .ivsize = NULL_IV_SIZE,
2179 .maxauthsize = SHA384_DIGEST_SIZE,
2180 },
2181 .caam = {
2182 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2183 OP_ALG_AAI_HMAC_PRECOMP,
2184 },
2185 },
2186 {
2187 .aead = {
2188 .base = {
2189 .cra_name = "authenc(hmac(sha512),"
2190 "ecb(cipher_null))",
2191 .cra_driver_name = "authenc-hmac-sha512-"
2192 "ecb-cipher_null-caam",
2193 .cra_blocksize = NULL_BLOCK_SIZE,
2194 },
2195 .setkey = aead_setkey,
2196 .setauthsize = aead_setauthsize,
2197 .encrypt = aead_encrypt,
2198 .decrypt = aead_decrypt,
2199 .ivsize = NULL_IV_SIZE,
2200 .maxauthsize = SHA512_DIGEST_SIZE,
2201 },
2202 .caam = {
2203 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2204 OP_ALG_AAI_HMAC_PRECOMP,
2205 },
2206 },
2207 {
2208 .aead = {
2209 .base = {
2210 .cra_name = "authenc(hmac(md5),cbc(aes))",
2211 .cra_driver_name = "authenc-hmac-md5-"
2212 "cbc-aes-caam",
2213 .cra_blocksize = AES_BLOCK_SIZE,
2214 },
2215 .setkey = aead_setkey,
2216 .setauthsize = aead_setauthsize,
2217 .encrypt = aead_encrypt,
2218 .decrypt = aead_decrypt,
2219 .ivsize = AES_BLOCK_SIZE,
2220 .maxauthsize = MD5_DIGEST_SIZE,
2221 },
2222 .caam = {
2223 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2224 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2225 OP_ALG_AAI_HMAC_PRECOMP,
2226 },
2227 },
2228 {
2229 .aead = {
2230 .base = {
2231 .cra_name = "echainiv(authenc(hmac(md5),"
2232 "cbc(aes)))",
2233 .cra_driver_name = "echainiv-authenc-hmac-md5-"
2234 "cbc-aes-caam",
2235 .cra_blocksize = AES_BLOCK_SIZE,
2236 },
2237 .setkey = aead_setkey,
2238 .setauthsize = aead_setauthsize,
2239 .encrypt = aead_encrypt,
2240 .decrypt = aead_decrypt,
2241 .ivsize = AES_BLOCK_SIZE,
2242 .maxauthsize = MD5_DIGEST_SIZE,
2243 },
2244 .caam = {
2245 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2246 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2247 OP_ALG_AAI_HMAC_PRECOMP,
2248 .geniv = true,
2249 },
2250 },
2251 {
2252 .aead = {
2253 .base = {
2254 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2255 .cra_driver_name = "authenc-hmac-sha1-"
2256 "cbc-aes-caam",
2257 .cra_blocksize = AES_BLOCK_SIZE,
2258 },
2259 .setkey = aead_setkey,
2260 .setauthsize = aead_setauthsize,
2261 .encrypt = aead_encrypt,
2262 .decrypt = aead_decrypt,
2263 .ivsize = AES_BLOCK_SIZE,
2264 .maxauthsize = SHA1_DIGEST_SIZE,
2265 },
2266 .caam = {
2267 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2268 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2269 OP_ALG_AAI_HMAC_PRECOMP,
2270 },
2271 },
2272 {
2273 .aead = {
2274 .base = {
2275 .cra_name = "echainiv(authenc(hmac(sha1),"
2276 "cbc(aes)))",
2277 .cra_driver_name = "echainiv-authenc-"
2278 "hmac-sha1-cbc-aes-caam",
2279 .cra_blocksize = AES_BLOCK_SIZE,
2280 },
2281 .setkey = aead_setkey,
2282 .setauthsize = aead_setauthsize,
2283 .encrypt = aead_encrypt,
2284 .decrypt = aead_decrypt,
2285 .ivsize = AES_BLOCK_SIZE,
2286 .maxauthsize = SHA1_DIGEST_SIZE,
2287 },
2288 .caam = {
2289 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2290 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2291 OP_ALG_AAI_HMAC_PRECOMP,
2292 .geniv = true,
2293 },
2294 },
2295 {
2296 .aead = {
2297 .base = {
2298 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2299 .cra_driver_name = "authenc-hmac-sha224-"
2300 "cbc-aes-caam",
2301 .cra_blocksize = AES_BLOCK_SIZE,
2302 },
2303 .setkey = aead_setkey,
2304 .setauthsize = aead_setauthsize,
2305 .encrypt = aead_encrypt,
2306 .decrypt = aead_decrypt,
2307 .ivsize = AES_BLOCK_SIZE,
2308 .maxauthsize = SHA224_DIGEST_SIZE,
2309 },
2310 .caam = {
2311 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2312 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2313 OP_ALG_AAI_HMAC_PRECOMP,
2314 },
2315 },
2316 {
2317 .aead = {
2318 .base = {
2319 .cra_name = "echainiv(authenc(hmac(sha224),"
2320 "cbc(aes)))",
2321 .cra_driver_name = "echainiv-authenc-"
2322 "hmac-sha224-cbc-aes-caam",
2323 .cra_blocksize = AES_BLOCK_SIZE,
2324 },
2325 .setkey = aead_setkey,
2326 .setauthsize = aead_setauthsize,
2327 .encrypt = aead_encrypt,
2328 .decrypt = aead_decrypt,
2329 .ivsize = AES_BLOCK_SIZE,
2330 .maxauthsize = SHA224_DIGEST_SIZE,
2331 },
2332 .caam = {
2333 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2334 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2335 OP_ALG_AAI_HMAC_PRECOMP,
2336 .geniv = true,
2337 },
2338 },
2339 {
2340 .aead = {
2341 .base = {
2342 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2343 .cra_driver_name = "authenc-hmac-sha256-"
2344 "cbc-aes-caam",
2345 .cra_blocksize = AES_BLOCK_SIZE,
2346 },
2347 .setkey = aead_setkey,
2348 .setauthsize = aead_setauthsize,
2349 .encrypt = aead_encrypt,
2350 .decrypt = aead_decrypt,
2351 .ivsize = AES_BLOCK_SIZE,
2352 .maxauthsize = SHA256_DIGEST_SIZE,
2353 },
2354 .caam = {
2355 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2356 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2357 OP_ALG_AAI_HMAC_PRECOMP,
2358 },
2359 },
2360 {
2361 .aead = {
2362 .base = {
2363 .cra_name = "echainiv(authenc(hmac(sha256),"
2364 "cbc(aes)))",
2365 .cra_driver_name = "echainiv-authenc-"
2366 "hmac-sha256-cbc-aes-caam",
2367 .cra_blocksize = AES_BLOCK_SIZE,
2368 },
2369 .setkey = aead_setkey,
2370 .setauthsize = aead_setauthsize,
2371 .encrypt = aead_encrypt,
2372 .decrypt = aead_decrypt,
2373 .ivsize = AES_BLOCK_SIZE,
2374 .maxauthsize = SHA256_DIGEST_SIZE,
2375 },
2376 .caam = {
2377 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2378 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2379 OP_ALG_AAI_HMAC_PRECOMP,
2380 .geniv = true,
2381 },
2382 },
2383 {
2384 .aead = {
2385 .base = {
2386 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2387 .cra_driver_name = "authenc-hmac-sha384-"
2388 "cbc-aes-caam",
2389 .cra_blocksize = AES_BLOCK_SIZE,
2390 },
2391 .setkey = aead_setkey,
2392 .setauthsize = aead_setauthsize,
2393 .encrypt = aead_encrypt,
2394 .decrypt = aead_decrypt,
2395 .ivsize = AES_BLOCK_SIZE,
2396 .maxauthsize = SHA384_DIGEST_SIZE,
2397 },
2398 .caam = {
2399 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2400 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2401 OP_ALG_AAI_HMAC_PRECOMP,
2402 },
2403 },
2404 {
2405 .aead = {
2406 .base = {
2407 .cra_name = "echainiv(authenc(hmac(sha384),"
2408 "cbc(aes)))",
2409 .cra_driver_name = "echainiv-authenc-"
2410 "hmac-sha384-cbc-aes-caam",
2411 .cra_blocksize = AES_BLOCK_SIZE,
2412 },
2413 .setkey = aead_setkey,
2414 .setauthsize = aead_setauthsize,
2415 .encrypt = aead_encrypt,
2416 .decrypt = aead_decrypt,
2417 .ivsize = AES_BLOCK_SIZE,
2418 .maxauthsize = SHA384_DIGEST_SIZE,
2419 },
2420 .caam = {
2421 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2422 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2423 OP_ALG_AAI_HMAC_PRECOMP,
2424 .geniv = true,
2425 },
2426 },
2427 {
2428 .aead = {
2429 .base = {
2430 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2431 .cra_driver_name = "authenc-hmac-sha512-"
2432 "cbc-aes-caam",
2433 .cra_blocksize = AES_BLOCK_SIZE,
2434 },
2435 .setkey = aead_setkey,
2436 .setauthsize = aead_setauthsize,
2437 .encrypt = aead_encrypt,
2438 .decrypt = aead_decrypt,
2439 .ivsize = AES_BLOCK_SIZE,
2440 .maxauthsize = SHA512_DIGEST_SIZE,
2441 },
2442 .caam = {
2443 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2444 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2445 OP_ALG_AAI_HMAC_PRECOMP,
2446 },
2447 },
2448 {
2449 .aead = {
2450 .base = {
2451 .cra_name = "echainiv(authenc(hmac(sha512),"
2452 "cbc(aes)))",
2453 .cra_driver_name = "echainiv-authenc-"
2454 "hmac-sha512-cbc-aes-caam",
2455 .cra_blocksize = AES_BLOCK_SIZE,
2456 },
2457 .setkey = aead_setkey,
2458 .setauthsize = aead_setauthsize,
2459 .encrypt = aead_encrypt,
2460 .decrypt = aead_decrypt,
2461 .ivsize = AES_BLOCK_SIZE,
2462 .maxauthsize = SHA512_DIGEST_SIZE,
2463 },
2464 .caam = {
2465 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2466 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2467 OP_ALG_AAI_HMAC_PRECOMP,
2468 .geniv = true,
2469 },
2470 },
2471 {
2472 .aead = {
2473 .base = {
2474 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2475 .cra_driver_name = "authenc-hmac-md5-"
2476 "cbc-des3_ede-caam",
2477 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2478 },
2479 .setkey = des3_aead_setkey,
2480 .setauthsize = aead_setauthsize,
2481 .encrypt = aead_encrypt,
2482 .decrypt = aead_decrypt,
2483 .ivsize = DES3_EDE_BLOCK_SIZE,
2484 .maxauthsize = MD5_DIGEST_SIZE,
2485 },
2486 .caam = {
2487 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2488 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2489 OP_ALG_AAI_HMAC_PRECOMP,
2490 }
2491 },
2492 {
2493 .aead = {
2494 .base = {
2495 .cra_name = "echainiv(authenc(hmac(md5),"
2496 "cbc(des3_ede)))",
2497 .cra_driver_name = "echainiv-authenc-hmac-md5-"
2498 "cbc-des3_ede-caam",
2499 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2500 },
2501 .setkey = des3_aead_setkey,
2502 .setauthsize = aead_setauthsize,
2503 .encrypt = aead_encrypt,
2504 .decrypt = aead_decrypt,
2505 .ivsize = DES3_EDE_BLOCK_SIZE,
2506 .maxauthsize = MD5_DIGEST_SIZE,
2507 },
2508 .caam = {
2509 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2510 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2511 OP_ALG_AAI_HMAC_PRECOMP,
2512 .geniv = true,
2513 }
2514 },
2515 {
2516 .aead = {
2517 .base = {
2518 .cra_name = "authenc(hmac(sha1),"
2519 "cbc(des3_ede))",
2520 .cra_driver_name = "authenc-hmac-sha1-"
2521 "cbc-des3_ede-caam",
2522 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2523 },
2524 .setkey = des3_aead_setkey,
2525 .setauthsize = aead_setauthsize,
2526 .encrypt = aead_encrypt,
2527 .decrypt = aead_decrypt,
2528 .ivsize = DES3_EDE_BLOCK_SIZE,
2529 .maxauthsize = SHA1_DIGEST_SIZE,
2530 },
2531 .caam = {
2532 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2533 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2534 OP_ALG_AAI_HMAC_PRECOMP,
2535 },
2536 },
2537 {
2538 .aead = {
2539 .base = {
2540 .cra_name = "echainiv(authenc(hmac(sha1),"
2541 "cbc(des3_ede)))",
2542 .cra_driver_name = "echainiv-authenc-"
2543 "hmac-sha1-"
2544 "cbc-des3_ede-caam",
2545 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2546 },
2547 .setkey = des3_aead_setkey,
2548 .setauthsize = aead_setauthsize,
2549 .encrypt = aead_encrypt,
2550 .decrypt = aead_decrypt,
2551 .ivsize = DES3_EDE_BLOCK_SIZE,
2552 .maxauthsize = SHA1_DIGEST_SIZE,
2553 },
2554 .caam = {
2555 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2556 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2557 OP_ALG_AAI_HMAC_PRECOMP,
2558 .geniv = true,
2559 },
2560 },
2561 {
2562 .aead = {
2563 .base = {
2564 .cra_name = "authenc(hmac(sha224),"
2565 "cbc(des3_ede))",
2566 .cra_driver_name = "authenc-hmac-sha224-"
2567 "cbc-des3_ede-caam",
2568 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2569 },
2570 .setkey = des3_aead_setkey,
2571 .setauthsize = aead_setauthsize,
2572 .encrypt = aead_encrypt,
2573 .decrypt = aead_decrypt,
2574 .ivsize = DES3_EDE_BLOCK_SIZE,
2575 .maxauthsize = SHA224_DIGEST_SIZE,
2576 },
2577 .caam = {
2578 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2579 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2580 OP_ALG_AAI_HMAC_PRECOMP,
2581 },
2582 },
2583 {
2584 .aead = {
2585 .base = {
2586 .cra_name = "echainiv(authenc(hmac(sha224),"
2587 "cbc(des3_ede)))",
2588 .cra_driver_name = "echainiv-authenc-"
2589 "hmac-sha224-"
2590 "cbc-des3_ede-caam",
2591 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2592 },
2593 .setkey = des3_aead_setkey,
2594 .setauthsize = aead_setauthsize,
2595 .encrypt = aead_encrypt,
2596 .decrypt = aead_decrypt,
2597 .ivsize = DES3_EDE_BLOCK_SIZE,
2598 .maxauthsize = SHA224_DIGEST_SIZE,
2599 },
2600 .caam = {
2601 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2602 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2603 OP_ALG_AAI_HMAC_PRECOMP,
2604 .geniv = true,
2605 },
2606 },
2607 {
2608 .aead = {
2609 .base = {
2610 .cra_name = "authenc(hmac(sha256),"
2611 "cbc(des3_ede))",
2612 .cra_driver_name = "authenc-hmac-sha256-"
2613 "cbc-des3_ede-caam",
2614 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2615 },
2616 .setkey = des3_aead_setkey,
2617 .setauthsize = aead_setauthsize,
2618 .encrypt = aead_encrypt,
2619 .decrypt = aead_decrypt,
2620 .ivsize = DES3_EDE_BLOCK_SIZE,
2621 .maxauthsize = SHA256_DIGEST_SIZE,
2622 },
2623 .caam = {
2624 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2625 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2626 OP_ALG_AAI_HMAC_PRECOMP,
2627 },
2628 },
2629 {
2630 .aead = {
2631 .base = {
2632 .cra_name = "echainiv(authenc(hmac(sha256),"
2633 "cbc(des3_ede)))",
2634 .cra_driver_name = "echainiv-authenc-"
2635 "hmac-sha256-"
2636 "cbc-des3_ede-caam",
2637 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2638 },
2639 .setkey = des3_aead_setkey,
2640 .setauthsize = aead_setauthsize,
2641 .encrypt = aead_encrypt,
2642 .decrypt = aead_decrypt,
2643 .ivsize = DES3_EDE_BLOCK_SIZE,
2644 .maxauthsize = SHA256_DIGEST_SIZE,
2645 },
2646 .caam = {
2647 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2648 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2649 OP_ALG_AAI_HMAC_PRECOMP,
2650 .geniv = true,
2651 },
2652 },
2653 {
2654 .aead = {
2655 .base = {
2656 .cra_name = "authenc(hmac(sha384),"
2657 "cbc(des3_ede))",
2658 .cra_driver_name = "authenc-hmac-sha384-"
2659 "cbc-des3_ede-caam",
2660 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2661 },
2662 .setkey = des3_aead_setkey,
2663 .setauthsize = aead_setauthsize,
2664 .encrypt = aead_encrypt,
2665 .decrypt = aead_decrypt,
2666 .ivsize = DES3_EDE_BLOCK_SIZE,
2667 .maxauthsize = SHA384_DIGEST_SIZE,
2668 },
2669 .caam = {
2670 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2671 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2672 OP_ALG_AAI_HMAC_PRECOMP,
2673 },
2674 },
2675 {
2676 .aead = {
2677 .base = {
2678 .cra_name = "echainiv(authenc(hmac(sha384),"
2679 "cbc(des3_ede)))",
2680 .cra_driver_name = "echainiv-authenc-"
2681 "hmac-sha384-"
2682 "cbc-des3_ede-caam",
2683 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2684 },
2685 .setkey = des3_aead_setkey,
2686 .setauthsize = aead_setauthsize,
2687 .encrypt = aead_encrypt,
2688 .decrypt = aead_decrypt,
2689 .ivsize = DES3_EDE_BLOCK_SIZE,
2690 .maxauthsize = SHA384_DIGEST_SIZE,
2691 },
2692 .caam = {
2693 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2694 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2695 OP_ALG_AAI_HMAC_PRECOMP,
2696 .geniv = true,
2697 },
2698 },
2699 {
2700 .aead = {
2701 .base = {
2702 .cra_name = "authenc(hmac(sha512),"
2703 "cbc(des3_ede))",
2704 .cra_driver_name = "authenc-hmac-sha512-"
2705 "cbc-des3_ede-caam",
2706 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2707 },
2708 .setkey = des3_aead_setkey,
2709 .setauthsize = aead_setauthsize,
2710 .encrypt = aead_encrypt,
2711 .decrypt = aead_decrypt,
2712 .ivsize = DES3_EDE_BLOCK_SIZE,
2713 .maxauthsize = SHA512_DIGEST_SIZE,
2714 },
2715 .caam = {
2716 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2717 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2718 OP_ALG_AAI_HMAC_PRECOMP,
2719 },
2720 },
2721 {
2722 .aead = {
2723 .base = {
2724 .cra_name = "echainiv(authenc(hmac(sha512),"
2725 "cbc(des3_ede)))",
2726 .cra_driver_name = "echainiv-authenc-"
2727 "hmac-sha512-"
2728 "cbc-des3_ede-caam",
2729 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2730 },
2731 .setkey = des3_aead_setkey,
2732 .setauthsize = aead_setauthsize,
2733 .encrypt = aead_encrypt,
2734 .decrypt = aead_decrypt,
2735 .ivsize = DES3_EDE_BLOCK_SIZE,
2736 .maxauthsize = SHA512_DIGEST_SIZE,
2737 },
2738 .caam = {
2739 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2740 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2741 OP_ALG_AAI_HMAC_PRECOMP,
2742 .geniv = true,
2743 },
2744 },
2745 {
2746 .aead = {
2747 .base = {
2748 .cra_name = "authenc(hmac(md5),cbc(des))",
2749 .cra_driver_name = "authenc-hmac-md5-"
2750 "cbc-des-caam",
2751 .cra_blocksize = DES_BLOCK_SIZE,
2752 },
2753 .setkey = aead_setkey,
2754 .setauthsize = aead_setauthsize,
2755 .encrypt = aead_encrypt,
2756 .decrypt = aead_decrypt,
2757 .ivsize = DES_BLOCK_SIZE,
2758 .maxauthsize = MD5_DIGEST_SIZE,
2759 },
2760 .caam = {
2761 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2762 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2763 OP_ALG_AAI_HMAC_PRECOMP,
2764 },
2765 },
2766 {
2767 .aead = {
2768 .base = {
2769 .cra_name = "echainiv(authenc(hmac(md5),"
2770 "cbc(des)))",
2771 .cra_driver_name = "echainiv-authenc-hmac-md5-"
2772 "cbc-des-caam",
2773 .cra_blocksize = DES_BLOCK_SIZE,
2774 },
2775 .setkey = aead_setkey,
2776 .setauthsize = aead_setauthsize,
2777 .encrypt = aead_encrypt,
2778 .decrypt = aead_decrypt,
2779 .ivsize = DES_BLOCK_SIZE,
2780 .maxauthsize = MD5_DIGEST_SIZE,
2781 },
2782 .caam = {
2783 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2784 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2785 OP_ALG_AAI_HMAC_PRECOMP,
2786 .geniv = true,
2787 },
2788 },
2789 {
2790 .aead = {
2791 .base = {
2792 .cra_name = "authenc(hmac(sha1),cbc(des))",
2793 .cra_driver_name = "authenc-hmac-sha1-"
2794 "cbc-des-caam",
2795 .cra_blocksize = DES_BLOCK_SIZE,
2796 },
2797 .setkey = aead_setkey,
2798 .setauthsize = aead_setauthsize,
2799 .encrypt = aead_encrypt,
2800 .decrypt = aead_decrypt,
2801 .ivsize = DES_BLOCK_SIZE,
2802 .maxauthsize = SHA1_DIGEST_SIZE,
2803 },
2804 .caam = {
2805 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2806 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2807 OP_ALG_AAI_HMAC_PRECOMP,
2808 },
2809 },
2810 {
2811 .aead = {
2812 .base = {
2813 .cra_name = "echainiv(authenc(hmac(sha1),"
2814 "cbc(des)))",
2815 .cra_driver_name = "echainiv-authenc-"
2816 "hmac-sha1-cbc-des-caam",
2817 .cra_blocksize = DES_BLOCK_SIZE,
2818 },
2819 .setkey = aead_setkey,
2820 .setauthsize = aead_setauthsize,
2821 .encrypt = aead_encrypt,
2822 .decrypt = aead_decrypt,
2823 .ivsize = DES_BLOCK_SIZE,
2824 .maxauthsize = SHA1_DIGEST_SIZE,
2825 },
2826 .caam = {
2827 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2828 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2829 OP_ALG_AAI_HMAC_PRECOMP,
2830 .geniv = true,
2831 },
2832 },
2833 {
2834 .aead = {
2835 .base = {
2836 .cra_name = "authenc(hmac(sha224),cbc(des))",
2837 .cra_driver_name = "authenc-hmac-sha224-"
2838 "cbc-des-caam",
2839 .cra_blocksize = DES_BLOCK_SIZE,
2840 },
2841 .setkey = aead_setkey,
2842 .setauthsize = aead_setauthsize,
2843 .encrypt = aead_encrypt,
2844 .decrypt = aead_decrypt,
2845 .ivsize = DES_BLOCK_SIZE,
2846 .maxauthsize = SHA224_DIGEST_SIZE,
2847 },
2848 .caam = {
2849 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2850 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2851 OP_ALG_AAI_HMAC_PRECOMP,
2852 },
2853 },
2854 {
2855 .aead = {
2856 .base = {
2857 .cra_name = "echainiv(authenc(hmac(sha224),"
2858 "cbc(des)))",
2859 .cra_driver_name = "echainiv-authenc-"
2860 "hmac-sha224-cbc-des-caam",
2861 .cra_blocksize = DES_BLOCK_SIZE,
2862 },
2863 .setkey = aead_setkey,
2864 .setauthsize = aead_setauthsize,
2865 .encrypt = aead_encrypt,
2866 .decrypt = aead_decrypt,
2867 .ivsize = DES_BLOCK_SIZE,
2868 .maxauthsize = SHA224_DIGEST_SIZE,
2869 },
2870 .caam = {
2871 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2872 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2873 OP_ALG_AAI_HMAC_PRECOMP,
2874 .geniv = true,
2875 },
2876 },
2877 {
2878 .aead = {
2879 .base = {
2880 .cra_name = "authenc(hmac(sha256),cbc(des))",
2881 .cra_driver_name = "authenc-hmac-sha256-"
2882 "cbc-des-caam",
2883 .cra_blocksize = DES_BLOCK_SIZE,
2884 },
2885 .setkey = aead_setkey,
2886 .setauthsize = aead_setauthsize,
2887 .encrypt = aead_encrypt,
2888 .decrypt = aead_decrypt,
2889 .ivsize = DES_BLOCK_SIZE,
2890 .maxauthsize = SHA256_DIGEST_SIZE,
2891 },
2892 .caam = {
2893 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2894 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2895 OP_ALG_AAI_HMAC_PRECOMP,
2896 },
2897 },
2898 {
2899 .aead = {
2900 .base = {
2901 .cra_name = "echainiv(authenc(hmac(sha256),"
2902 "cbc(des)))",
2903 .cra_driver_name = "echainiv-authenc-"
2904 "hmac-sha256-cbc-des-caam",
2905 .cra_blocksize = DES_BLOCK_SIZE,
2906 },
2907 .setkey = aead_setkey,
2908 .setauthsize = aead_setauthsize,
2909 .encrypt = aead_encrypt,
2910 .decrypt = aead_decrypt,
2911 .ivsize = DES_BLOCK_SIZE,
2912 .maxauthsize = SHA256_DIGEST_SIZE,
2913 },
2914 .caam = {
2915 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2916 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2917 OP_ALG_AAI_HMAC_PRECOMP,
2918 .geniv = true,
2919 },
2920 },
2921 {
2922 .aead = {
2923 .base = {
2924 .cra_name = "authenc(hmac(sha384),cbc(des))",
2925 .cra_driver_name = "authenc-hmac-sha384-"
2926 "cbc-des-caam",
2927 .cra_blocksize = DES_BLOCK_SIZE,
2928 },
2929 .setkey = aead_setkey,
2930 .setauthsize = aead_setauthsize,
2931 .encrypt = aead_encrypt,
2932 .decrypt = aead_decrypt,
2933 .ivsize = DES_BLOCK_SIZE,
2934 .maxauthsize = SHA384_DIGEST_SIZE,
2935 },
2936 .caam = {
2937 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2938 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2939 OP_ALG_AAI_HMAC_PRECOMP,
2940 },
2941 },
2942 {
2943 .aead = {
2944 .base = {
2945 .cra_name = "echainiv(authenc(hmac(sha384),"
2946 "cbc(des)))",
2947 .cra_driver_name = "echainiv-authenc-"
2948 "hmac-sha384-cbc-des-caam",
2949 .cra_blocksize = DES_BLOCK_SIZE,
2950 },
2951 .setkey = aead_setkey,
2952 .setauthsize = aead_setauthsize,
2953 .encrypt = aead_encrypt,
2954 .decrypt = aead_decrypt,
2955 .ivsize = DES_BLOCK_SIZE,
2956 .maxauthsize = SHA384_DIGEST_SIZE,
2957 },
2958 .caam = {
2959 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2960 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2961 OP_ALG_AAI_HMAC_PRECOMP,
2962 .geniv = true,
2963 },
2964 },
2965 {
2966 .aead = {
2967 .base = {
2968 .cra_name = "authenc(hmac(sha512),cbc(des))",
2969 .cra_driver_name = "authenc-hmac-sha512-"
2970 "cbc-des-caam",
2971 .cra_blocksize = DES_BLOCK_SIZE,
2972 },
2973 .setkey = aead_setkey,
2974 .setauthsize = aead_setauthsize,
2975 .encrypt = aead_encrypt,
2976 .decrypt = aead_decrypt,
2977 .ivsize = DES_BLOCK_SIZE,
2978 .maxauthsize = SHA512_DIGEST_SIZE,
2979 },
2980 .caam = {
2981 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2982 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2983 OP_ALG_AAI_HMAC_PRECOMP,
2984 },
2985 },
2986 {
2987 .aead = {
2988 .base = {
2989 .cra_name = "echainiv(authenc(hmac(sha512),"
2990 "cbc(des)))",
2991 .cra_driver_name = "echainiv-authenc-"
2992 "hmac-sha512-cbc-des-caam",
2993 .cra_blocksize = DES_BLOCK_SIZE,
2994 },
2995 .setkey = aead_setkey,
2996 .setauthsize = aead_setauthsize,
2997 .encrypt = aead_encrypt,
2998 .decrypt = aead_decrypt,
2999 .ivsize = DES_BLOCK_SIZE,
3000 .maxauthsize = SHA512_DIGEST_SIZE,
3001 },
3002 .caam = {
3003 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
3004 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
3005 OP_ALG_AAI_HMAC_PRECOMP,
3006 .geniv = true,
3007 },
3008 },
3009 {
3010 .aead = {
3011 .base = {
3012 .cra_name = "authenc(hmac(md5),"
3013 "rfc3686(ctr(aes)))",
3014 .cra_driver_name = "authenc-hmac-md5-"
3015 "rfc3686-ctr-aes-caam",
3016 .cra_blocksize = 1,
3017 },
3018 .setkey = aead_setkey,
3019 .setauthsize = aead_setauthsize,
3020 .encrypt = aead_encrypt,
3021 .decrypt = aead_decrypt,
3022 .ivsize = CTR_RFC3686_IV_SIZE,
3023 .maxauthsize = MD5_DIGEST_SIZE,
3024 },
3025 .caam = {
3026 .class1_alg_type = OP_ALG_ALGSEL_AES |
3027 OP_ALG_AAI_CTR_MOD128,
3028 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
3029 OP_ALG_AAI_HMAC_PRECOMP,
3030 .rfc3686 = true,
3031 },
3032 },
3033 {
3034 .aead = {
3035 .base = {
3036 .cra_name = "seqiv(authenc("
3037 "hmac(md5),rfc3686(ctr(aes))))",
3038 .cra_driver_name = "seqiv-authenc-hmac-md5-"
3039 "rfc3686-ctr-aes-caam",
3040 .cra_blocksize = 1,
3041 },
3042 .setkey = aead_setkey,
3043 .setauthsize = aead_setauthsize,
3044 .encrypt = aead_encrypt,
3045 .decrypt = aead_decrypt,
3046 .ivsize = CTR_RFC3686_IV_SIZE,
3047 .maxauthsize = MD5_DIGEST_SIZE,
3048 },
3049 .caam = {
3050 .class1_alg_type = OP_ALG_ALGSEL_AES |
3051 OP_ALG_AAI_CTR_MOD128,
3052 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
3053 OP_ALG_AAI_HMAC_PRECOMP,
3054 .rfc3686 = true,
3055 .geniv = true,
3056 },
3057 },
3058 {
3059 .aead = {
3060 .base = {
3061 .cra_name = "authenc(hmac(sha1),"
3062 "rfc3686(ctr(aes)))",
3063 .cra_driver_name = "authenc-hmac-sha1-"
3064 "rfc3686-ctr-aes-caam",
3065 .cra_blocksize = 1,
3066 },
3067 .setkey = aead_setkey,
3068 .setauthsize = aead_setauthsize,
3069 .encrypt = aead_encrypt,
3070 .decrypt = aead_decrypt,
3071 .ivsize = CTR_RFC3686_IV_SIZE,
3072 .maxauthsize = SHA1_DIGEST_SIZE,
3073 },
3074 .caam = {
3075 .class1_alg_type = OP_ALG_ALGSEL_AES |
3076 OP_ALG_AAI_CTR_MOD128,
3077 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
3078 OP_ALG_AAI_HMAC_PRECOMP,
3079 .rfc3686 = true,
3080 },
3081 },
3082 {
3083 .aead = {
3084 .base = {
3085 .cra_name = "seqiv(authenc("
3086 "hmac(sha1),rfc3686(ctr(aes))))",
3087 .cra_driver_name = "seqiv-authenc-hmac-sha1-"
3088 "rfc3686-ctr-aes-caam",
3089 .cra_blocksize = 1,
3090 },
3091 .setkey = aead_setkey,
3092 .setauthsize = aead_setauthsize,
3093 .encrypt = aead_encrypt,
3094 .decrypt = aead_decrypt,
3095 .ivsize = CTR_RFC3686_IV_SIZE,
3096 .maxauthsize = SHA1_DIGEST_SIZE,
3097 },
3098 .caam = {
3099 .class1_alg_type = OP_ALG_ALGSEL_AES |
3100 OP_ALG_AAI_CTR_MOD128,
3101 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
3102 OP_ALG_AAI_HMAC_PRECOMP,
3103 .rfc3686 = true,
3104 .geniv = true,
3105 },
3106 },
3107 {
3108 .aead = {
3109 .base = {
3110 .cra_name = "authenc(hmac(sha224),"
3111 "rfc3686(ctr(aes)))",
3112 .cra_driver_name = "authenc-hmac-sha224-"
3113 "rfc3686-ctr-aes-caam",
3114 .cra_blocksize = 1,
3115 },
3116 .setkey = aead_setkey,
3117 .setauthsize = aead_setauthsize,
3118 .encrypt = aead_encrypt,
3119 .decrypt = aead_decrypt,
3120 .ivsize = CTR_RFC3686_IV_SIZE,
3121 .maxauthsize = SHA224_DIGEST_SIZE,
3122 },
3123 .caam = {
3124 .class1_alg_type = OP_ALG_ALGSEL_AES |
3125 OP_ALG_AAI_CTR_MOD128,
3126 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
3127 OP_ALG_AAI_HMAC_PRECOMP,
3128 .rfc3686 = true,
3129 },
3130 },
3131 {
3132 .aead = {
3133 .base = {
3134 .cra_name = "seqiv(authenc("
3135 "hmac(sha224),rfc3686(ctr(aes))))",
3136 .cra_driver_name = "seqiv-authenc-hmac-sha224-"
3137 "rfc3686-ctr-aes-caam",
3138 .cra_blocksize = 1,
3139 },
3140 .setkey = aead_setkey,
3141 .setauthsize = aead_setauthsize,
3142 .encrypt = aead_encrypt,
3143 .decrypt = aead_decrypt,
3144 .ivsize = CTR_RFC3686_IV_SIZE,
3145 .maxauthsize = SHA224_DIGEST_SIZE,
3146 },
3147 .caam = {
3148 .class1_alg_type = OP_ALG_ALGSEL_AES |
3149 OP_ALG_AAI_CTR_MOD128,
3150 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
3151 OP_ALG_AAI_HMAC_PRECOMP,
3152 .rfc3686 = true,
3153 .geniv = true,
3154 },
3155 },
3156 {
3157 .aead = {
3158 .base = {
3159 .cra_name = "authenc(hmac(sha256),"
3160 "rfc3686(ctr(aes)))",
3161 .cra_driver_name = "authenc-hmac-sha256-"
3162 "rfc3686-ctr-aes-caam",
3163 .cra_blocksize = 1,
3164 },
3165 .setkey = aead_setkey,
3166 .setauthsize = aead_setauthsize,
3167 .encrypt = aead_encrypt,
3168 .decrypt = aead_decrypt,
3169 .ivsize = CTR_RFC3686_IV_SIZE,
3170 .maxauthsize = SHA256_DIGEST_SIZE,
3171 },
3172 .caam = {
3173 .class1_alg_type = OP_ALG_ALGSEL_AES |
3174 OP_ALG_AAI_CTR_MOD128,
3175 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
3176 OP_ALG_AAI_HMAC_PRECOMP,
3177 .rfc3686 = true,
3178 },
3179 },
3180 {
3181 .aead = {
3182 .base = {
3183 .cra_name = "seqiv(authenc(hmac(sha256),"
3184 "rfc3686(ctr(aes))))",
3185 .cra_driver_name = "seqiv-authenc-hmac-sha256-"
3186 "rfc3686-ctr-aes-caam",
3187 .cra_blocksize = 1,
3188 },
3189 .setkey = aead_setkey,
3190 .setauthsize = aead_setauthsize,
3191 .encrypt = aead_encrypt,
3192 .decrypt = aead_decrypt,
3193 .ivsize = CTR_RFC3686_IV_SIZE,
3194 .maxauthsize = SHA256_DIGEST_SIZE,
3195 },
3196 .caam = {
3197 .class1_alg_type = OP_ALG_ALGSEL_AES |
3198 OP_ALG_AAI_CTR_MOD128,
3199 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
3200 OP_ALG_AAI_HMAC_PRECOMP,
3201 .rfc3686 = true,
3202 .geniv = true,
3203 },
3204 },
3205 {
3206 .aead = {
3207 .base = {
3208 .cra_name = "authenc(hmac(sha384),"
3209 "rfc3686(ctr(aes)))",
3210 .cra_driver_name = "authenc-hmac-sha384-"
3211 "rfc3686-ctr-aes-caam",
3212 .cra_blocksize = 1,
3213 },
3214 .setkey = aead_setkey,
3215 .setauthsize = aead_setauthsize,
3216 .encrypt = aead_encrypt,
3217 .decrypt = aead_decrypt,
3218 .ivsize = CTR_RFC3686_IV_SIZE,
3219 .maxauthsize = SHA384_DIGEST_SIZE,
3220 },
3221 .caam = {
3222 .class1_alg_type = OP_ALG_ALGSEL_AES |
3223 OP_ALG_AAI_CTR_MOD128,
3224 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
3225 OP_ALG_AAI_HMAC_PRECOMP,
3226 .rfc3686 = true,
3227 },
3228 },
3229 {
3230 .aead = {
3231 .base = {
3232 .cra_name = "seqiv(authenc(hmac(sha384),"
3233 "rfc3686(ctr(aes))))",
3234 .cra_driver_name = "seqiv-authenc-hmac-sha384-"
3235 "rfc3686-ctr-aes-caam",
3236 .cra_blocksize = 1,
3237 },
3238 .setkey = aead_setkey,
3239 .setauthsize = aead_setauthsize,
3240 .encrypt = aead_encrypt,
3241 .decrypt = aead_decrypt,
3242 .ivsize = CTR_RFC3686_IV_SIZE,
3243 .maxauthsize = SHA384_DIGEST_SIZE,
3244 },
3245 .caam = {
3246 .class1_alg_type = OP_ALG_ALGSEL_AES |
3247 OP_ALG_AAI_CTR_MOD128,
3248 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
3249 OP_ALG_AAI_HMAC_PRECOMP,
3250 .rfc3686 = true,
3251 .geniv = true,
3252 },
3253 },
3254 {
3255 .aead = {
3256 .base = {
3257 .cra_name = "authenc(hmac(sha512),"
3258 "rfc3686(ctr(aes)))",
3259 .cra_driver_name = "authenc-hmac-sha512-"
3260 "rfc3686-ctr-aes-caam",
3261 .cra_blocksize = 1,
3262 },
3263 .setkey = aead_setkey,
3264 .setauthsize = aead_setauthsize,
3265 .encrypt = aead_encrypt,
3266 .decrypt = aead_decrypt,
3267 .ivsize = CTR_RFC3686_IV_SIZE,
3268 .maxauthsize = SHA512_DIGEST_SIZE,
3269 },
3270 .caam = {
3271 .class1_alg_type = OP_ALG_ALGSEL_AES |
3272 OP_ALG_AAI_CTR_MOD128,
3273 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
3274 OP_ALG_AAI_HMAC_PRECOMP,
3275 .rfc3686 = true,
3276 },
3277 },
3278 {
3279 .aead = {
3280 .base = {
3281 .cra_name = "seqiv(authenc(hmac(sha512),"
3282 "rfc3686(ctr(aes))))",
3283 .cra_driver_name = "seqiv-authenc-hmac-sha512-"
3284 "rfc3686-ctr-aes-caam",
3285 .cra_blocksize = 1,
3286 },
3287 .setkey = aead_setkey,
3288 .setauthsize = aead_setauthsize,
3289 .encrypt = aead_encrypt,
3290 .decrypt = aead_decrypt,
3291 .ivsize = CTR_RFC3686_IV_SIZE,
3292 .maxauthsize = SHA512_DIGEST_SIZE,
3293 },
3294 .caam = {
3295 .class1_alg_type = OP_ALG_ALGSEL_AES |
3296 OP_ALG_AAI_CTR_MOD128,
3297 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
3298 OP_ALG_AAI_HMAC_PRECOMP,
3299 .rfc3686 = true,
3300 .geniv = true,
3301 },
3302 },
3303 {
3304 .aead = {
3305 .base = {
3306 .cra_name = "rfc7539(chacha20,poly1305)",
3307 .cra_driver_name = "rfc7539-chacha20-poly1305-"
3308 "caam",
3309 .cra_blocksize = 1,
3310 },
3311 .setkey = chachapoly_setkey,
3312 .setauthsize = chachapoly_setauthsize,
3313 .encrypt = chachapoly_encrypt,
3314 .decrypt = chachapoly_decrypt,
3315 .ivsize = CHACHAPOLY_IV_SIZE,
3316 .maxauthsize = POLY1305_DIGEST_SIZE,
3317 },
3318 .caam = {
3319 .class1_alg_type = OP_ALG_ALGSEL_CHACHA20 |
3320 OP_ALG_AAI_AEAD,
3321 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
3322 OP_ALG_AAI_AEAD,
3323 .nodkp = true,
3324 },
3325 },
3326 {
3327 .aead = {
3328 .base = {
3329 .cra_name = "rfc7539esp(chacha20,poly1305)",
3330 .cra_driver_name = "rfc7539esp-chacha20-"
3331 "poly1305-caam",
3332 .cra_blocksize = 1,
3333 },
3334 .setkey = chachapoly_setkey,
3335 .setauthsize = chachapoly_setauthsize,
3336 .encrypt = chachapoly_encrypt,
3337 .decrypt = chachapoly_decrypt,
3338 .ivsize = 8,
3339 .maxauthsize = POLY1305_DIGEST_SIZE,
3340 },
3341 .caam = {
3342 .class1_alg_type = OP_ALG_ALGSEL_CHACHA20 |
3343 OP_ALG_AAI_AEAD,
3344 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
3345 OP_ALG_AAI_AEAD,
3346 .nodkp = true,
3347 },
3348 },
3349 };
3350
caam_init_common(struct caam_ctx * ctx,struct caam_alg_entry * caam,bool uses_dkp)3351 static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam,
3352 bool uses_dkp)
3353 {
3354 dma_addr_t dma_addr;
3355 struct caam_drv_private *priv;
3356 const size_t sh_desc_enc_offset = offsetof(struct caam_ctx,
3357 sh_desc_enc);
3358
3359 ctx->jrdev = caam_jr_alloc();
3360 if (IS_ERR(ctx->jrdev)) {
3361 pr_err("Job Ring Device allocation for transform failed\n");
3362 return PTR_ERR(ctx->jrdev);
3363 }
3364
3365 priv = dev_get_drvdata(ctx->jrdev->parent);
3366 if (priv->era >= 6 && uses_dkp)
3367 ctx->dir = DMA_BIDIRECTIONAL;
3368 else
3369 ctx->dir = DMA_TO_DEVICE;
3370
3371 dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_enc,
3372 offsetof(struct caam_ctx,
3373 sh_desc_enc_dma) -
3374 sh_desc_enc_offset,
3375 ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
3376 if (dma_mapping_error(ctx->jrdev, dma_addr)) {
3377 dev_err(ctx->jrdev, "unable to map key, shared descriptors\n");
3378 caam_jr_free(ctx->jrdev);
3379 return -ENOMEM;
3380 }
3381
3382 ctx->sh_desc_enc_dma = dma_addr;
3383 ctx->sh_desc_dec_dma = dma_addr + offsetof(struct caam_ctx,
3384 sh_desc_dec) -
3385 sh_desc_enc_offset;
3386 ctx->key_dma = dma_addr + offsetof(struct caam_ctx, key) -
3387 sh_desc_enc_offset;
3388
3389 /* copy descriptor header template value */
3390 ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
3391 ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
3392
3393 return 0;
3394 }
3395
caam_cra_init(struct crypto_skcipher * tfm)3396 static int caam_cra_init(struct crypto_skcipher *tfm)
3397 {
3398 struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
3399 struct caam_skcipher_alg *caam_alg =
3400 container_of(alg, typeof(*caam_alg), skcipher);
3401 struct caam_ctx *ctx = crypto_skcipher_ctx(tfm);
3402 u32 alg_aai = caam_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
3403 int ret = 0;
3404
3405 ctx->enginectx.op.do_one_request = skcipher_do_one_req;
3406
3407 if (alg_aai == OP_ALG_AAI_XTS) {
3408 const char *tfm_name = crypto_tfm_alg_name(&tfm->base);
3409 struct crypto_skcipher *fallback;
3410
3411 fallback = crypto_alloc_skcipher(tfm_name, 0,
3412 CRYPTO_ALG_NEED_FALLBACK);
3413 if (IS_ERR(fallback)) {
3414 pr_err("Failed to allocate %s fallback: %ld\n",
3415 tfm_name, PTR_ERR(fallback));
3416 return PTR_ERR(fallback);
3417 }
3418
3419 ctx->fallback = fallback;
3420 crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_skcipher_req_ctx) +
3421 crypto_skcipher_reqsize(fallback));
3422 } else {
3423 crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_skcipher_req_ctx));
3424 }
3425
3426 ret = caam_init_common(ctx, &caam_alg->caam, false);
3427 if (ret && ctx->fallback)
3428 crypto_free_skcipher(ctx->fallback);
3429
3430 return ret;
3431 }
3432
caam_aead_init(struct crypto_aead * tfm)3433 static int caam_aead_init(struct crypto_aead *tfm)
3434 {
3435 struct aead_alg *alg = crypto_aead_alg(tfm);
3436 struct caam_aead_alg *caam_alg =
3437 container_of(alg, struct caam_aead_alg, aead);
3438 struct caam_ctx *ctx = crypto_aead_ctx(tfm);
3439
3440 crypto_aead_set_reqsize(tfm, sizeof(struct caam_aead_req_ctx));
3441
3442 ctx->enginectx.op.do_one_request = aead_do_one_req;
3443
3444 return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp);
3445 }
3446
caam_exit_common(struct caam_ctx * ctx)3447 static void caam_exit_common(struct caam_ctx *ctx)
3448 {
3449 dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_enc_dma,
3450 offsetof(struct caam_ctx, sh_desc_enc_dma) -
3451 offsetof(struct caam_ctx, sh_desc_enc),
3452 ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
3453 caam_jr_free(ctx->jrdev);
3454 }
3455
caam_cra_exit(struct crypto_skcipher * tfm)3456 static void caam_cra_exit(struct crypto_skcipher *tfm)
3457 {
3458 struct caam_ctx *ctx = crypto_skcipher_ctx(tfm);
3459
3460 if (ctx->fallback)
3461 crypto_free_skcipher(ctx->fallback);
3462 caam_exit_common(ctx);
3463 }
3464
caam_aead_exit(struct crypto_aead * tfm)3465 static void caam_aead_exit(struct crypto_aead *tfm)
3466 {
3467 caam_exit_common(crypto_aead_ctx(tfm));
3468 }
3469
caam_algapi_exit(void)3470 void caam_algapi_exit(void)
3471 {
3472 int i;
3473
3474 for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
3475 struct caam_aead_alg *t_alg = driver_aeads + i;
3476
3477 if (t_alg->registered)
3478 crypto_unregister_aead(&t_alg->aead);
3479 }
3480
3481 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
3482 struct caam_skcipher_alg *t_alg = driver_algs + i;
3483
3484 if (t_alg->registered)
3485 crypto_unregister_skcipher(&t_alg->skcipher);
3486 }
3487 }
3488
caam_skcipher_alg_init(struct caam_skcipher_alg * t_alg)3489 static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg)
3490 {
3491 struct skcipher_alg *alg = &t_alg->skcipher;
3492
3493 alg->base.cra_module = THIS_MODULE;
3494 alg->base.cra_priority = CAAM_CRA_PRIORITY;
3495 alg->base.cra_ctxsize = sizeof(struct caam_ctx);
3496 alg->base.cra_flags |= (CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
3497 CRYPTO_ALG_KERN_DRIVER_ONLY);
3498
3499 alg->init = caam_cra_init;
3500 alg->exit = caam_cra_exit;
3501 }
3502
caam_aead_alg_init(struct caam_aead_alg * t_alg)3503 static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
3504 {
3505 struct aead_alg *alg = &t_alg->aead;
3506
3507 alg->base.cra_module = THIS_MODULE;
3508 alg->base.cra_priority = CAAM_CRA_PRIORITY;
3509 alg->base.cra_ctxsize = sizeof(struct caam_ctx);
3510 alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
3511 CRYPTO_ALG_KERN_DRIVER_ONLY;
3512
3513 alg->init = caam_aead_init;
3514 alg->exit = caam_aead_exit;
3515 }
3516
caam_algapi_init(struct device * ctrldev)3517 int caam_algapi_init(struct device *ctrldev)
3518 {
3519 struct caam_drv_private *priv = dev_get_drvdata(ctrldev);
3520 int i = 0, err = 0;
3521 u32 aes_vid, aes_inst, des_inst, md_vid, md_inst, ccha_inst, ptha_inst;
3522 unsigned int md_limit = SHA512_DIGEST_SIZE;
3523 bool registered = false, gcm_support;
3524
3525 /*
3526 * Register crypto algorithms the device supports.
3527 * First, detect presence and attributes of DES, AES, and MD blocks.
3528 */
3529 if (priv->era < 10) {
3530 u32 cha_vid, cha_inst, aes_rn;
3531
3532 cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
3533 aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
3534 md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
3535
3536 cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
3537 des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>
3538 CHA_ID_LS_DES_SHIFT;
3539 aes_inst = cha_inst & CHA_ID_LS_AES_MASK;
3540 md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
3541 ccha_inst = 0;
3542 ptha_inst = 0;
3543
3544 aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) &
3545 CHA_ID_LS_AES_MASK;
3546 gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8);
3547 } else {
3548 u32 aesa, mdha;
3549
3550 aesa = rd_reg32(&priv->ctrl->vreg.aesa);
3551 mdha = rd_reg32(&priv->ctrl->vreg.mdha);
3552
3553 aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
3554 md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
3555
3556 des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
3557 aes_inst = aesa & CHA_VER_NUM_MASK;
3558 md_inst = mdha & CHA_VER_NUM_MASK;
3559 ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK;
3560 ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK;
3561
3562 gcm_support = aesa & CHA_VER_MISC_AES_GCM;
3563 }
3564
3565 /* If MD is present, limit digest size based on LP256 */
3566 if (md_inst && md_vid == CHA_VER_VID_MD_LP256)
3567 md_limit = SHA256_DIGEST_SIZE;
3568
3569 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
3570 struct caam_skcipher_alg *t_alg = driver_algs + i;
3571 u32 alg_sel = t_alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK;
3572
3573 /* Skip DES algorithms if not supported by device */
3574 if (!des_inst &&
3575 ((alg_sel == OP_ALG_ALGSEL_3DES) ||
3576 (alg_sel == OP_ALG_ALGSEL_DES)))
3577 continue;
3578
3579 /* Skip AES algorithms if not supported by device */
3580 if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES))
3581 continue;
3582
3583 /*
3584 * Check support for AES modes not available
3585 * on LP devices.
3586 */
3587 if (aes_vid == CHA_VER_VID_AES_LP &&
3588 (t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK) ==
3589 OP_ALG_AAI_XTS)
3590 continue;
3591
3592 caam_skcipher_alg_init(t_alg);
3593
3594 err = crypto_register_skcipher(&t_alg->skcipher);
3595 if (err) {
3596 pr_warn("%s alg registration failed\n",
3597 t_alg->skcipher.base.cra_driver_name);
3598 continue;
3599 }
3600
3601 t_alg->registered = true;
3602 registered = true;
3603 }
3604
3605 for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
3606 struct caam_aead_alg *t_alg = driver_aeads + i;
3607 u32 c1_alg_sel = t_alg->caam.class1_alg_type &
3608 OP_ALG_ALGSEL_MASK;
3609 u32 c2_alg_sel = t_alg->caam.class2_alg_type &
3610 OP_ALG_ALGSEL_MASK;
3611 u32 alg_aai = t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
3612
3613 /* Skip DES algorithms if not supported by device */
3614 if (!des_inst &&
3615 ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
3616 (c1_alg_sel == OP_ALG_ALGSEL_DES)))
3617 continue;
3618
3619 /* Skip AES algorithms if not supported by device */
3620 if (!aes_inst && (c1_alg_sel == OP_ALG_ALGSEL_AES))
3621 continue;
3622
3623 /* Skip CHACHA20 algorithms if not supported by device */
3624 if (c1_alg_sel == OP_ALG_ALGSEL_CHACHA20 && !ccha_inst)
3625 continue;
3626
3627 /* Skip POLY1305 algorithms if not supported by device */
3628 if (c2_alg_sel == OP_ALG_ALGSEL_POLY1305 && !ptha_inst)
3629 continue;
3630
3631 /* Skip GCM algorithms if not supported by device */
3632 if (c1_alg_sel == OP_ALG_ALGSEL_AES &&
3633 alg_aai == OP_ALG_AAI_GCM && !gcm_support)
3634 continue;
3635
3636 /*
3637 * Skip algorithms requiring message digests
3638 * if MD or MD size is not supported by device.
3639 */
3640 if (is_mdha(c2_alg_sel) &&
3641 (!md_inst || t_alg->aead.maxauthsize > md_limit))
3642 continue;
3643
3644 caam_aead_alg_init(t_alg);
3645
3646 err = crypto_register_aead(&t_alg->aead);
3647 if (err) {
3648 pr_warn("%s alg registration failed\n",
3649 t_alg->aead.base.cra_driver_name);
3650 continue;
3651 }
3652
3653 t_alg->registered = true;
3654 registered = true;
3655 }
3656
3657 if (registered)
3658 pr_info("caam algorithms registered in /proc/crypto\n");
3659
3660 return err;
3661 }
3662