1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59
60 #define MLX5_ADEV_NAME "mlx5_core"
61
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64 enum {
65 MLX5_BOARD_ID_LEN = 64,
66 };
67
68 enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70 };
71
72 enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76 };
77
78 enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84 };
85
86 enum {
87 MLX5_MAX_PORTS = 4,
88 };
89
90 enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100 };
101
102 enum {
103 MLX5_REG_QPTS = 0x4002,
104 MLX5_REG_QETCR = 0x4005,
105 MLX5_REG_QTCT = 0x400a,
106 MLX5_REG_QPDPM = 0x4013,
107 MLX5_REG_QCAM = 0x4019,
108 MLX5_REG_DCBX_PARAM = 0x4020,
109 MLX5_REG_DCBX_APP = 0x4021,
110 MLX5_REG_FPGA_CAP = 0x4022,
111 MLX5_REG_FPGA_CTRL = 0x4023,
112 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 MLX5_REG_CORE_DUMP = 0x402e,
114 MLX5_REG_PCAP = 0x5001,
115 MLX5_REG_PMTU = 0x5003,
116 MLX5_REG_PTYS = 0x5004,
117 MLX5_REG_PAOS = 0x5006,
118 MLX5_REG_PFCC = 0x5007,
119 MLX5_REG_PPCNT = 0x5008,
120 MLX5_REG_PPTB = 0x500b,
121 MLX5_REG_PBMC = 0x500c,
122 MLX5_REG_PMAOS = 0x5012,
123 MLX5_REG_PUDE = 0x5009,
124 MLX5_REG_PMPE = 0x5010,
125 MLX5_REG_PELC = 0x500e,
126 MLX5_REG_PVLC = 0x500f,
127 MLX5_REG_PCMR = 0x5041,
128 MLX5_REG_PDDR = 0x5031,
129 MLX5_REG_PMLP = 0x5002,
130 MLX5_REG_PPLM = 0x5023,
131 MLX5_REG_PCAM = 0x507f,
132 MLX5_REG_NODE_DESC = 0x6001,
133 MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 MLX5_REG_MCIA = 0x9014,
135 MLX5_REG_MFRL = 0x9028,
136 MLX5_REG_MLCR = 0x902b,
137 MLX5_REG_MRTC = 0x902d,
138 MLX5_REG_MTRC_CAP = 0x9040,
139 MLX5_REG_MTRC_CONF = 0x9041,
140 MLX5_REG_MTRC_STDB = 0x9042,
141 MLX5_REG_MTRC_CTRL = 0x9043,
142 MLX5_REG_MPEIN = 0x9050,
143 MLX5_REG_MPCNT = 0x9051,
144 MLX5_REG_MTPPS = 0x9053,
145 MLX5_REG_MTPPSE = 0x9054,
146 MLX5_REG_MTUTC = 0x9055,
147 MLX5_REG_MPEGC = 0x9056,
148 MLX5_REG_MCQS = 0x9060,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 MLX5_REG_MIRC = 0x9162,
154 MLX5_REG_SBCAM = 0xB01F,
155 MLX5_REG_RESOURCE_DUMP = 0xC000,
156 MLX5_REG_DTOR = 0xC00E,
157 };
158
159 enum mlx5_qpts_trust_state {
160 MLX5_QPTS_TRUST_PCP = 1,
161 MLX5_QPTS_TRUST_DSCP = 2,
162 };
163
164 enum mlx5_dcbx_oper_mode {
165 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
166 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
167 };
168
169 enum {
170 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
171 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
174 };
175
176 enum mlx5_page_fault_resume_flags {
177 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
179 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
180 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
181 };
182
183 enum dbg_rsc_type {
184 MLX5_DBG_RSC_QP,
185 MLX5_DBG_RSC_EQ,
186 MLX5_DBG_RSC_CQ,
187 };
188
189 enum port_state_policy {
190 MLX5_POLICY_DOWN = 0,
191 MLX5_POLICY_UP = 1,
192 MLX5_POLICY_FOLLOW = 2,
193 MLX5_POLICY_INVALID = 0xffffffff
194 };
195
196 enum mlx5_coredev_type {
197 MLX5_COREDEV_PF,
198 MLX5_COREDEV_VF,
199 MLX5_COREDEV_SF,
200 };
201
202 struct mlx5_field_desc {
203 int i;
204 };
205
206 struct mlx5_rsc_debug {
207 struct mlx5_core_dev *dev;
208 void *object;
209 enum dbg_rsc_type type;
210 struct dentry *root;
211 struct mlx5_field_desc fields[];
212 };
213
214 enum mlx5_dev_event {
215 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
216 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
217 };
218
219 enum mlx5_port_status {
220 MLX5_PORT_UP = 1,
221 MLX5_PORT_DOWN = 2,
222 };
223
224 enum mlx5_cmdif_state {
225 MLX5_CMDIF_STATE_UNINITIALIZED,
226 MLX5_CMDIF_STATE_UP,
227 MLX5_CMDIF_STATE_DOWN,
228 };
229
230 struct mlx5_cmd_first {
231 __be32 data[4];
232 };
233
234 struct mlx5_cmd_msg {
235 struct list_head list;
236 struct cmd_msg_cache *parent;
237 u32 len;
238 struct mlx5_cmd_first first;
239 struct mlx5_cmd_mailbox *next;
240 };
241
242 struct mlx5_cmd_debug {
243 struct dentry *dbg_root;
244 void *in_msg;
245 void *out_msg;
246 u8 status;
247 u16 inlen;
248 u16 outlen;
249 };
250
251 struct cmd_msg_cache {
252 /* protect block chain allocations
253 */
254 spinlock_t lock;
255 struct list_head head;
256 unsigned int max_inbox_size;
257 unsigned int num_ent;
258 };
259
260 enum {
261 MLX5_NUM_COMMAND_CACHES = 5,
262 };
263
264 struct mlx5_cmd_stats {
265 u64 sum;
266 u64 n;
267 /* number of times command failed */
268 u64 failed;
269 /* number of times command failed on bad status returned by FW */
270 u64 failed_mbox_status;
271 /* last command failed returned errno */
272 u32 last_failed_errno;
273 /* last bad status returned by FW */
274 u8 last_failed_mbox_status;
275 /* last command failed syndrome returned by FW */
276 u32 last_failed_syndrome;
277 struct dentry *root;
278 /* protect command average calculations */
279 spinlock_t lock;
280 };
281
282 struct mlx5_cmd {
283 struct mlx5_nb nb;
284
285 /* members which needs to be queried or reinitialized each reload */
286 struct {
287 u16 cmdif_rev;
288 u8 log_sz;
289 u8 log_stride;
290 int max_reg_cmds;
291 unsigned long bitmask;
292 struct semaphore sem;
293 struct semaphore pages_sem;
294 struct semaphore throttle_sem;
295 } vars;
296 enum mlx5_cmdif_state state;
297 void *cmd_alloc_buf;
298 dma_addr_t alloc_dma;
299 int alloc_size;
300 void *cmd_buf;
301 dma_addr_t dma;
302
303 /* protect command queue allocations
304 */
305 spinlock_t alloc_lock;
306
307 /* protect token allocations
308 */
309 spinlock_t token_lock;
310 u8 token;
311 char wq_name[MLX5_CMD_WQ_MAX_NAME];
312 struct workqueue_struct *wq;
313 int mode;
314 u16 allowed_opcode;
315 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
316 struct dma_pool *pool;
317 struct mlx5_cmd_debug dbg;
318 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
319 int checksum_disabled;
320 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
321 };
322
323 struct mlx5_cmd_mailbox {
324 void *buf;
325 dma_addr_t dma;
326 struct mlx5_cmd_mailbox *next;
327 };
328
329 struct mlx5_buf_list {
330 void *buf;
331 dma_addr_t map;
332 };
333
334 struct mlx5_frag_buf {
335 struct mlx5_buf_list *frags;
336 int npages;
337 int size;
338 u8 page_shift;
339 };
340
341 struct mlx5_frag_buf_ctrl {
342 struct mlx5_buf_list *frags;
343 u32 sz_m1;
344 u16 frag_sz_m1;
345 u16 strides_offset;
346 u8 log_sz;
347 u8 log_stride;
348 u8 log_frag_strides;
349 };
350
351 struct mlx5_core_psv {
352 u32 psv_idx;
353 struct psv_layout {
354 u32 pd;
355 u16 syndrome;
356 u16 reserved;
357 u16 bg;
358 u16 app_tag;
359 u32 ref_tag;
360 } psv;
361 };
362
363 struct mlx5_core_sig_ctx {
364 struct mlx5_core_psv psv_memory;
365 struct mlx5_core_psv psv_wire;
366 struct ib_sig_err err_item;
367 bool sig_status_checked;
368 bool sig_err_exists;
369 u32 sigerr_count;
370 };
371
372 #define MLX5_24BIT_MASK ((1 << 24) - 1)
373
374 enum mlx5_res_type {
375 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
376 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
377 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
378 MLX5_RES_SRQ = 3,
379 MLX5_RES_XSRQ = 4,
380 MLX5_RES_XRQ = 5,
381 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
382 };
383
384 struct mlx5_core_rsc_common {
385 enum mlx5_res_type res;
386 refcount_t refcount;
387 struct completion free;
388 };
389
390 struct mlx5_uars_page {
391 void __iomem *map;
392 bool wc;
393 u32 index;
394 struct list_head list;
395 unsigned int bfregs;
396 unsigned long *reg_bitmap; /* for non fast path bf regs */
397 unsigned long *fp_bitmap;
398 unsigned int reg_avail;
399 unsigned int fp_avail;
400 struct kref ref_count;
401 struct mlx5_core_dev *mdev;
402 };
403
404 struct mlx5_bfreg_head {
405 /* protect blue flame registers allocations */
406 struct mutex lock;
407 struct list_head list;
408 };
409
410 struct mlx5_bfreg_data {
411 struct mlx5_bfreg_head reg_head;
412 struct mlx5_bfreg_head wc_head;
413 };
414
415 struct mlx5_sq_bfreg {
416 void __iomem *map;
417 struct mlx5_uars_page *up;
418 bool wc;
419 u32 index;
420 unsigned int offset;
421 };
422
423 struct mlx5_core_health {
424 struct health_buffer __iomem *health;
425 __be32 __iomem *health_counter;
426 struct timer_list timer;
427 u32 prev;
428 int miss_counter;
429 u8 synd;
430 u32 fatal_error;
431 u32 crdump_size;
432 /* wq spinlock to synchronize draining */
433 spinlock_t wq_lock;
434 struct workqueue_struct *wq;
435 unsigned long flags;
436 struct work_struct fatal_report_work;
437 struct work_struct report_work;
438 struct devlink_health_reporter *fw_reporter;
439 struct devlink_health_reporter *fw_fatal_reporter;
440 struct delayed_work update_fw_log_ts_work;
441 };
442
443 struct mlx5_qp_table {
444 struct notifier_block nb;
445
446 /* protect radix tree
447 */
448 spinlock_t lock;
449 struct radix_tree_root tree;
450 };
451
452 enum {
453 MLX5_PF_NOTIFY_DISABLE_VF,
454 MLX5_PF_NOTIFY_ENABLE_VF,
455 };
456
457 struct mlx5_vf_context {
458 int enabled;
459 u64 port_guid;
460 u64 node_guid;
461 /* Valid bits are used to validate administrative guid only.
462 * Enabled after ndo_set_vf_guid
463 */
464 u8 port_guid_valid:1;
465 u8 node_guid_valid:1;
466 enum port_state_policy policy;
467 struct blocking_notifier_head notifier;
468 };
469
470 struct mlx5_core_sriov {
471 struct mlx5_vf_context *vfs_ctx;
472 int num_vfs;
473 u16 max_vfs;
474 };
475
476 struct mlx5_fc_pool {
477 struct mlx5_core_dev *dev;
478 struct mutex pool_lock; /* protects pool lists */
479 struct list_head fully_used;
480 struct list_head partially_used;
481 struct list_head unused;
482 int available_fcs;
483 int used_fcs;
484 int threshold;
485 };
486
487 struct mlx5_fc_stats {
488 spinlock_t counters_idr_lock; /* protects counters_idr */
489 struct idr counters_idr;
490 struct list_head counters;
491 struct llist_head addlist;
492 struct llist_head dellist;
493
494 struct workqueue_struct *wq;
495 struct delayed_work work;
496 unsigned long next_query;
497 unsigned long sampling_interval; /* jiffies */
498 u32 *bulk_query_out;
499 int bulk_query_len;
500 size_t num_counters;
501 bool bulk_query_alloc_failed;
502 unsigned long next_bulk_query_alloc;
503 struct mlx5_fc_pool fc_pool;
504 };
505
506 struct mlx5_events;
507 struct mlx5_mpfs;
508 struct mlx5_eswitch;
509 struct mlx5_lag;
510 struct mlx5_devcom;
511 struct mlx5_fw_reset;
512 struct mlx5_eq_table;
513 struct mlx5_irq_table;
514 struct mlx5_vhca_state_notifier;
515 struct mlx5_sf_dev_table;
516 struct mlx5_sf_hw_table;
517 struct mlx5_sf_table;
518
519 struct mlx5_rate_limit {
520 u32 rate;
521 u32 max_burst_sz;
522 u16 typical_pkt_sz;
523 };
524
525 struct mlx5_rl_entry {
526 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
527 u64 refcount;
528 u16 index;
529 u16 uid;
530 u8 dedicated : 1;
531 };
532
533 struct mlx5_rl_table {
534 /* protect rate limit table */
535 struct mutex rl_lock;
536 u16 max_size;
537 u32 max_rate;
538 u32 min_rate;
539 struct mlx5_rl_entry *rl_entry;
540 u64 refcount;
541 };
542
543 struct mlx5_core_roce {
544 struct mlx5_flow_table *ft;
545 struct mlx5_flow_group *fg;
546 struct mlx5_flow_handle *allow_rule;
547 };
548
549 enum {
550 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
551 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
552 /* Set during device detach to block any further devices
553 * creation/deletion on drivers rescan. Unset during device attach.
554 */
555 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
556 /* Distinguish between mlx5e_probe/remove called by module init/cleanup
557 * and called by other flows which can already hold devlink lock
558 */
559 MLX5_PRIV_FLAGS_MLX5E_LOCKED_FLOW = 1 << 3,
560 };
561
562 struct mlx5_adev {
563 struct auxiliary_device adev;
564 struct mlx5_core_dev *mdev;
565 int idx;
566 };
567
568 struct mlx5_debugfs_entries {
569 struct dentry *dbg_root;
570 struct dentry *qp_debugfs;
571 struct dentry *eq_debugfs;
572 struct dentry *cq_debugfs;
573 struct dentry *cmdif_debugfs;
574 struct dentry *pages_debugfs;
575 struct dentry *lag_debugfs;
576 };
577
578 enum mlx5_func_type {
579 MLX5_PF,
580 MLX5_VF,
581 MLX5_SF,
582 MLX5_HOST_PF,
583 MLX5_FUNC_TYPE_NUM,
584 };
585
586 struct mlx5_ft_pool;
587 struct mlx5_priv {
588 /* IRQ table valid only for real pci devices PF or VF */
589 struct mlx5_irq_table *irq_table;
590 struct mlx5_eq_table *eq_table;
591
592 /* pages stuff */
593 struct mlx5_nb pg_nb;
594 struct workqueue_struct *pg_wq;
595 struct xarray page_root_xa;
596 atomic_t reg_pages;
597 struct list_head free_list;
598 u32 fw_pages;
599 u32 page_counters[MLX5_FUNC_TYPE_NUM];
600 u32 fw_pages_alloc_failed;
601 u32 give_pages_dropped;
602 u32 reclaim_pages_discard;
603
604 struct mlx5_core_health health;
605 struct list_head traps;
606
607 struct mlx5_debugfs_entries dbg;
608
609 /* start: alloc staff */
610 /* protect buffer allocation according to numa node */
611 struct mutex alloc_mutex;
612 int numa_node;
613
614 struct mutex pgdir_mutex;
615 struct list_head pgdir_list;
616 /* end: alloc staff */
617
618 struct list_head ctx_list;
619 spinlock_t ctx_lock;
620 struct mlx5_adev **adev;
621 int adev_idx;
622 int sw_vhca_id;
623 struct mlx5_events *events;
624
625 struct mlx5_flow_steering *steering;
626 struct mlx5_mpfs *mpfs;
627 struct mlx5_eswitch *eswitch;
628 struct mlx5_core_sriov sriov;
629 struct mlx5_lag *lag;
630 u32 flags;
631 struct mlx5_devcom *devcom;
632 struct mlx5_fw_reset *fw_reset;
633 struct mlx5_core_roce roce;
634 struct mlx5_fc_stats fc_stats;
635 struct mlx5_rl_table rl_table;
636 struct mlx5_ft_pool *ft_pool;
637
638 struct mlx5_bfreg_data bfregs;
639 struct mlx5_uars_page *uar;
640 #ifdef CONFIG_MLX5_SF
641 struct mlx5_vhca_state_notifier *vhca_state_notifier;
642 struct mlx5_sf_dev_table *sf_dev_table;
643 struct mlx5_core_dev *parent_mdev;
644 #endif
645 #ifdef CONFIG_MLX5_SF_MANAGER
646 struct mlx5_sf_hw_table *sf_hw_table;
647 struct mlx5_sf_table *sf_table;
648 #endif
649 };
650
651 enum mlx5_device_state {
652 MLX5_DEVICE_STATE_UP = 1,
653 MLX5_DEVICE_STATE_INTERNAL_ERROR,
654 };
655
656 enum mlx5_interface_state {
657 MLX5_INTERFACE_STATE_UP = BIT(0),
658 MLX5_BREAK_FW_WAIT = BIT(1),
659 };
660
661 enum mlx5_pci_status {
662 MLX5_PCI_STATUS_DISABLED,
663 MLX5_PCI_STATUS_ENABLED,
664 };
665
666 enum mlx5_pagefault_type_flags {
667 MLX5_PFAULT_REQUESTOR = 1 << 0,
668 MLX5_PFAULT_WRITE = 1 << 1,
669 MLX5_PFAULT_RDMA = 1 << 2,
670 };
671
672 struct mlx5_td {
673 /* protects tirs list changes while tirs refresh */
674 struct mutex list_lock;
675 struct list_head tirs_list;
676 u32 tdn;
677 };
678
679 struct mlx5e_resources {
680 struct mlx5e_hw_objs {
681 u32 pdn;
682 struct mlx5_td td;
683 u32 mkey;
684 struct mlx5_sq_bfreg bfreg;
685 } hw_objs;
686 struct devlink_port dl_port;
687 struct net_device *uplink_netdev;
688 };
689
690 enum mlx5_sw_icm_type {
691 MLX5_SW_ICM_TYPE_STEERING,
692 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
693 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
694 };
695
696 #define MLX5_MAX_RESERVED_GIDS 8
697
698 struct mlx5_rsvd_gids {
699 unsigned int start;
700 unsigned int count;
701 struct ida ida;
702 };
703
704 #define MAX_PIN_NUM 8
705 struct mlx5_pps {
706 u8 pin_caps[MAX_PIN_NUM];
707 struct work_struct out_work;
708 u64 start[MAX_PIN_NUM];
709 u8 enabled;
710 u64 min_npps_period;
711 u64 min_out_pulse_duration_ns;
712 };
713
714 struct mlx5_timer {
715 struct cyclecounter cycles;
716 struct timecounter tc;
717 u32 nominal_c_mult;
718 unsigned long overflow_period;
719 struct delayed_work overflow_work;
720 };
721
722 struct mlx5_clock {
723 struct mlx5_nb pps_nb;
724 seqlock_t lock;
725 struct hwtstamp_config hwtstamp_config;
726 struct ptp_clock *ptp;
727 struct ptp_clock_info ptp_info;
728 struct mlx5_pps pps_info;
729 struct mlx5_timer timer;
730 };
731
732 struct mlx5_dm;
733 struct mlx5_fw_tracer;
734 struct mlx5_vxlan;
735 struct mlx5_geneve;
736 struct mlx5_hv_vhca;
737
738 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
739 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
740
741 enum {
742 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
743 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
744 };
745
746 enum {
747 MKEY_CACHE_LAST_STD_ENTRY = 20,
748 MLX5_IMR_MTT_CACHE_ENTRY,
749 MLX5_IMR_KSM_CACHE_ENTRY,
750 MAX_MKEY_CACHE_ENTRIES
751 };
752
753 struct mlx5_profile {
754 u64 mask;
755 u8 log_max_qp;
756 struct {
757 int size;
758 int limit;
759 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
760 };
761
762 struct mlx5_hca_cap {
763 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
764 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
765 };
766
767 struct mlx5_core_dev {
768 struct device *device;
769 enum mlx5_coredev_type coredev_type;
770 struct pci_dev *pdev;
771 /* sync pci state */
772 struct mutex pci_status_mutex;
773 enum mlx5_pci_status pci_status;
774 u8 rev_id;
775 char board_id[MLX5_BOARD_ID_LEN];
776 struct mlx5_cmd cmd;
777 struct {
778 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
779 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
780 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
781 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
782 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
783 u8 embedded_cpu;
784 } caps;
785 struct mlx5_timeouts *timeouts;
786 u64 sys_image_guid;
787 phys_addr_t iseg_base;
788 struct mlx5_init_seg __iomem *iseg;
789 phys_addr_t bar_addr;
790 enum mlx5_device_state state;
791 /* sync interface state */
792 struct mutex intf_state_mutex;
793 struct lock_class_key lock_key;
794 unsigned long intf_state;
795 struct mlx5_priv priv;
796 struct mlx5_profile profile;
797 u32 issi;
798 struct mlx5e_resources mlx5e_res;
799 struct mlx5_dm *dm;
800 struct mlx5_vxlan *vxlan;
801 struct mlx5_geneve *geneve;
802 struct {
803 struct mlx5_rsvd_gids reserved_gids;
804 u32 roce_en;
805 } roce;
806 #ifdef CONFIG_MLX5_FPGA
807 struct mlx5_fpga_device *fpga;
808 #endif
809 struct mlx5_clock clock;
810 struct mlx5_ib_clock_info *clock_info;
811 struct mlx5_fw_tracer *tracer;
812 struct mlx5_rsc_dump *rsc_dump;
813 u32 vsc_addr;
814 struct mlx5_hv_vhca *hv_vhca;
815 };
816
817 struct mlx5_db {
818 __be32 *db;
819 union {
820 struct mlx5_db_pgdir *pgdir;
821 struct mlx5_ib_user_db_page *user_page;
822 } u;
823 dma_addr_t dma;
824 int index;
825 };
826
827 enum {
828 MLX5_COMP_EQ_SIZE = 1024,
829 };
830
831 enum {
832 MLX5_PTYS_IB = 1 << 0,
833 MLX5_PTYS_EN = 1 << 2,
834 };
835
836 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
837
838 enum {
839 MLX5_CMD_ENT_STATE_PENDING_COMP,
840 };
841
842 struct mlx5_cmd_work_ent {
843 unsigned long state;
844 struct mlx5_cmd_msg *in;
845 struct mlx5_cmd_msg *out;
846 void *uout;
847 int uout_size;
848 mlx5_cmd_cbk_t callback;
849 struct delayed_work cb_timeout_work;
850 void *context;
851 int idx;
852 struct completion handling;
853 struct completion done;
854 struct mlx5_cmd *cmd;
855 struct work_struct work;
856 struct mlx5_cmd_layout *lay;
857 int ret;
858 int page_queue;
859 u8 status;
860 u8 token;
861 u64 ts1;
862 u64 ts2;
863 u16 op;
864 bool polling;
865 /* Track the max comp handlers */
866 refcount_t refcnt;
867 };
868
869 enum phy_port_state {
870 MLX5_AAA_111
871 };
872
873 struct mlx5_hca_vport_context {
874 u32 field_select;
875 bool sm_virt_aware;
876 bool has_smi;
877 bool has_raw;
878 enum port_state_policy policy;
879 enum phy_port_state phys_state;
880 enum ib_port_state vport_state;
881 u8 port_physical_state;
882 u64 sys_image_guid;
883 u64 port_guid;
884 u64 node_guid;
885 u32 cap_mask1;
886 u32 cap_mask1_perm;
887 u16 cap_mask2;
888 u16 cap_mask2_perm;
889 u16 lid;
890 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
891 u8 lmc;
892 u8 subnet_timeout;
893 u16 sm_lid;
894 u8 sm_sl;
895 u16 qkey_violation_counter;
896 u16 pkey_violation_counter;
897 bool grh_required;
898 };
899
900 #define STRUCT_FIELD(header, field) \
901 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
902 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
903
904 extern struct dentry *mlx5_debugfs_root;
905
fw_rev_maj(struct mlx5_core_dev * dev)906 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
907 {
908 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
909 }
910
fw_rev_min(struct mlx5_core_dev * dev)911 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
912 {
913 return ioread32be(&dev->iseg->fw_rev) >> 16;
914 }
915
fw_rev_sub(struct mlx5_core_dev * dev)916 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
917 {
918 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
919 }
920
mlx5_base_mkey(const u32 key)921 static inline u32 mlx5_base_mkey(const u32 key)
922 {
923 return key & 0xffffff00u;
924 }
925
wq_get_byte_sz(u8 log_sz,u8 log_stride)926 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
927 {
928 return ((u32)1 << log_sz) << log_stride;
929 }
930
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)931 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
932 u8 log_stride, u8 log_sz,
933 u16 strides_offset,
934 struct mlx5_frag_buf_ctrl *fbc)
935 {
936 fbc->frags = frags;
937 fbc->log_stride = log_stride;
938 fbc->log_sz = log_sz;
939 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
940 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
941 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
942 fbc->strides_offset = strides_offset;
943 }
944
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)945 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
946 u8 log_stride, u8 log_sz,
947 struct mlx5_frag_buf_ctrl *fbc)
948 {
949 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
950 }
951
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)952 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
953 u32 ix)
954 {
955 unsigned int frag;
956
957 ix += fbc->strides_offset;
958 frag = ix >> fbc->log_frag_strides;
959
960 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
961 }
962
963 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)964 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
965 {
966 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
967
968 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
969 }
970
971 enum {
972 CMD_ALLOWED_OPCODE_ALL,
973 };
974
975 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
976 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
977 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
978
979 struct mlx5_async_ctx {
980 struct mlx5_core_dev *dev;
981 atomic_t num_inflight;
982 struct completion inflight_done;
983 };
984
985 struct mlx5_async_work;
986
987 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
988
989 struct mlx5_async_work {
990 struct mlx5_async_ctx *ctx;
991 mlx5_async_cbk_t user_callback;
992 u16 opcode; /* cmd opcode */
993 u16 op_mod; /* cmd op_mod */
994 void *out; /* pointer to the cmd output buffer */
995 };
996
997 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
998 struct mlx5_async_ctx *ctx);
999 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
1000 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1001 void *out, int out_size, mlx5_async_cbk_t callback,
1002 struct mlx5_async_work *work);
1003 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1004 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1005 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1006 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1007 int out_size);
1008
1009 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1010 ({ \
1011 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1012 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1013 })
1014
1015 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1016 ({ \
1017 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1018 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1019 })
1020
1021 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1022 void *out, int out_size);
1023 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1024
1025 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1026 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1027 int mlx5_health_init(struct mlx5_core_dev *dev);
1028 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1029 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1030 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1031 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1032 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1033 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1034 struct mlx5_frag_buf *buf, int node);
1035 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1036 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1037 gfp_t flags, int npages);
1038 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1039 struct mlx5_cmd_mailbox *head);
1040 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1041 int inlen);
1042 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1043 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1044 int outlen);
1045 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1046 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1047 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1048 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1049 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1050 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1051 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1052 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1053 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1054 s32 npages, bool ec_function);
1055 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1056 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1057 void mlx5_register_debugfs(void);
1058 void mlx5_unregister_debugfs(void);
1059
1060 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1061 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1062 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1063 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1064 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1065
1066 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1067 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1068 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1069 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1070 void *data_out, int size_out, u16 reg_id, int arg,
1071 int write, bool verbose);
1072 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1073 int size_in, void *data_out, int size_out,
1074 u16 reg_num, int arg, int write);
1075
1076 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1077 int node);
1078
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1079 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1080 {
1081 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1082 }
1083
1084 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1085
1086 const char *mlx5_command_str(int command);
1087 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1088 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1089 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1090 int npsvs, u32 *sig_index);
1091 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1092 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1093 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1094 struct mlx5_odp_caps *odp_caps);
1095
1096 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1097 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1098 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1099 struct mlx5_rate_limit *rl);
1100 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1101 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1102 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1103 bool dedicated_entry, u16 *index);
1104 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1105 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1106 struct mlx5_rate_limit *rl_1);
1107 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1108 bool map_wc, bool fast_path);
1109 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1110
1111 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1112 struct cpumask *
1113 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1114 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1115 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1116 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1117 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1118
mlx5_mkey_to_idx(u32 mkey)1119 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1120 {
1121 return mkey >> 8;
1122 }
1123
mlx5_idx_to_mkey(u32 mkey_idx)1124 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1125 {
1126 return mkey_idx << 8;
1127 }
1128
mlx5_mkey_variant(u32 mkey)1129 static inline u8 mlx5_mkey_variant(u32 mkey)
1130 {
1131 return mkey & 0xff;
1132 }
1133
1134 /* Async-atomic event notifier used by mlx5 core to forward FW
1135 * evetns received from event queue to mlx5 consumers.
1136 * Optimise event queue dipatching.
1137 */
1138 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1139 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1140
1141 /* Async-atomic event notifier used for forwarding
1142 * evetns from the event queue into the to mlx5 events dispatcher,
1143 * eswitch, clock and others.
1144 */
1145 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1146 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1147
1148 /* Blocking event notifier used to forward SW events, used for slow path */
1149 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1150 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1151 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1152 void *data);
1153
1154 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1155
1156 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1157 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1158 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1159 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1160 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1161 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1162 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1163 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1164 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1165 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1166 struct net_device *slave);
1167 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1168 u64 *values,
1169 int num_counters,
1170 size_t *offsets);
1171 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1172 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1173 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1174 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1175 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1176 u64 length, u32 log_alignment, u16 uid,
1177 phys_addr_t *addr, u32 *obj_id);
1178 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1179 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1180
1181 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1182 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1183
1184 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1185 int vf_id,
1186 struct notifier_block *nb);
1187 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1188 int vf_id,
1189 struct notifier_block *nb);
1190 #ifdef CONFIG_MLX5_CORE_IPOIB
1191 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1192 struct ib_device *ibdev,
1193 const char *name,
1194 void (*setup)(struct net_device *));
1195 #endif /* CONFIG_MLX5_CORE_IPOIB */
1196 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1197 struct ib_device *device,
1198 struct rdma_netdev_alloc_params *params);
1199
1200 enum {
1201 MLX5_PCI_DEV_IS_VF = 1 << 0,
1202 };
1203
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1204 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1205 {
1206 return dev->coredev_type == MLX5_COREDEV_PF;
1207 }
1208
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1209 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1210 {
1211 return dev->coredev_type == MLX5_COREDEV_VF;
1212 }
1213
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1214 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1215 {
1216 return dev->caps.embedded_cpu;
1217 }
1218
1219 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1220 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1221 {
1222 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1223 }
1224
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1225 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1226 {
1227 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1228 }
1229
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1230 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1231 {
1232 return dev->priv.sriov.max_vfs;
1233 }
1234
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1235 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1236 {
1237 /* LACP owner conditions:
1238 * 1) Function is physical.
1239 * 2) LAG is supported by FW.
1240 * 3) LAG is managed by driver (currently the only option).
1241 */
1242 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1243 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1244 MLX5_CAP_GEN(dev, lag_master);
1245 }
1246
mlx5_get_gid_table_len(u16 param)1247 static inline int mlx5_get_gid_table_len(u16 param)
1248 {
1249 if (param > 4) {
1250 pr_warn("gid table length is zero\n");
1251 return 0;
1252 }
1253
1254 return 8 * (1 << param);
1255 }
1256
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1257 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1258 {
1259 return !!(dev->priv.rl_table.max_size);
1260 }
1261
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1262 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1263 {
1264 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1265 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1266 }
1267
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1268 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1269 {
1270 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1271 }
1272
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1273 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1274 {
1275 return mlx5_core_is_mp_slave(dev) ||
1276 mlx5_core_is_mp_master(dev);
1277 }
1278
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1279 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1280 {
1281 if (!mlx5_core_mp_enabled(dev))
1282 return 1;
1283
1284 return MLX5_CAP_GEN(dev, native_port_num);
1285 }
1286
mlx5_get_dev_index(struct mlx5_core_dev * dev)1287 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1288 {
1289 int idx = MLX5_CAP_GEN(dev, native_port_num);
1290
1291 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1292 return idx - 1;
1293 else
1294 return PCI_FUNC(dev->pdev->devfn);
1295 }
1296
1297 enum {
1298 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1299 };
1300
1301 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1302
mlx5_get_roce_state(struct mlx5_core_dev * dev)1303 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1304 {
1305 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1306 return MLX5_CAP_GEN(dev, roce);
1307
1308 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1309 * in order to support RoCE enable/disable feature
1310 */
1311 return mlx5_is_roce_on(dev);
1312 }
1313
1314 enum {
1315 MLX5_OCTWORD = 16,
1316 };
1317
1318 #endif /* MLX5_DRIVER_H */
1319