1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G2L CPG driver 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/r9a07g044-cpg.h> 14 #include <dt-bindings/clock/r9a07g054-cpg.h> 15 16 #include "rzg2l-cpg.h" 17 18 enum clk_ids { 19 /* Core Clock Outputs exported to DT */ 20 LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, 21 22 /* External Input Clocks */ 23 CLK_EXTAL, 24 25 /* Internal Core Clocks */ 26 CLK_OSC_DIV1000, 27 CLK_PLL1, 28 CLK_PLL2, 29 CLK_PLL2_DIV2, 30 CLK_PLL2_DIV2_8, 31 CLK_PLL2_DIV2_10, 32 CLK_PLL3, 33 CLK_PLL3_400, 34 CLK_PLL3_533, 35 CLK_M2_DIV2, 36 CLK_PLL3_DIV2, 37 CLK_PLL3_DIV2_2, 38 CLK_PLL3_DIV2_4, 39 CLK_PLL3_DIV2_4_2, 40 CLK_SEL_PLL3_3, 41 CLK_DIV_PLL3_C, 42 CLK_PLL4, 43 CLK_PLL5, 44 CLK_PLL5_FOUTPOSTDIV, 45 CLK_PLL5_FOUT1PH0, 46 CLK_PLL5_FOUT3, 47 CLK_PLL5_250, 48 CLK_PLL6, 49 CLK_PLL6_250, 50 CLK_P1_DIV2, 51 CLK_PLL2_800, 52 CLK_PLL2_SDHI_533, 53 CLK_PLL2_SDHI_400, 54 CLK_PLL2_SDHI_266, 55 CLK_SD0_DIV4, 56 CLK_SD1_DIV4, 57 CLK_SEL_GPU2, 58 CLK_SEL_PLL5_4, 59 CLK_DSI_DIV, 60 CLK_PLL2_533, 61 CLK_PLL2_533_DIV2, 62 CLK_DIV_DSI_LPCLK, 63 64 /* Module Clocks */ 65 MOD_CLK_BASE, 66 }; 67 68 /* Divider tables */ 69 static const struct clk_div_table dtable_1_8[] = { 70 {0, 1}, 71 {1, 2}, 72 {2, 4}, 73 {3, 8}, 74 {0, 0}, 75 }; 76 77 static const struct clk_div_table dtable_1_32[] = { 78 {0, 1}, 79 {1, 2}, 80 {2, 4}, 81 {3, 8}, 82 {4, 32}, 83 {0, 0}, 84 }; 85 86 static const struct clk_div_table dtable_16_128[] = { 87 {0, 16}, 88 {1, 32}, 89 {2, 64}, 90 {3, 128}, 91 {0, 0}, 92 }; 93 94 /* Mux clock tables */ 95 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 96 static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; 97 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 98 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 99 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; 100 101 static const struct { 102 struct cpg_core_clk common[56]; 103 #ifdef CONFIG_CLK_R9A07G054 104 struct cpg_core_clk drp[0]; 105 #endif 106 } core_clks __initconst = { 107 .common = { 108 /* External Clock Inputs */ 109 DEF_INPUT("extal", CLK_EXTAL), 110 111 /* Internal Core Clocks */ 112 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), 113 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 114 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 115 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 116 DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3), 117 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 118 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), 119 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), 120 121 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 122 DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), 123 124 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 125 126 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 127 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 128 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), 129 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), 130 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), 131 132 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 133 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), 134 135 DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2), 136 137 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 138 DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), 139 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 140 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 141 DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), 142 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), 143 144 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), 145 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 146 DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2), 147 DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), 148 DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), 149 DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4), 150 DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2, 151 DIVDSILPCLK, dtable_16_128), 152 153 /* Core output clk */ 154 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), 155 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), 156 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), 157 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), 158 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), 159 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), 160 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), 161 DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 162 DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 163 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), 164 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 165 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 166 DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi), 167 DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi), 168 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), 169 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), 170 DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8), 171 DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), 172 DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2), 173 DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), 174 DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT), 175 DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1), 176 DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1), 177 }, 178 #ifdef CONFIG_CLK_R9A07G054 179 .drp = { 180 }, 181 #endif 182 }; 183 184 static const struct { 185 struct rzg2l_mod_clk common[76]; 186 #ifdef CONFIG_CLK_R9A07G054 187 struct rzg2l_mod_clk drp[0]; 188 #endif 189 } mod_clks = { 190 .common = { 191 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, 192 0x514, 0), 193 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, 194 0x518, 0), 195 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 196 0x518, 1), 197 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, 198 0x52c, 0), 199 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, 200 0x52c, 1), 201 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, 202 0x534, 0), 203 DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, 204 0x534, 1), 205 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 206 0x534, 2), 207 DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 208 0x540, 0), 209 DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, 210 0x544, 0), 211 DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0, 212 0x544, 1), 213 DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0, 214 0x544, 2), 215 DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0, 216 0x544, 3), 217 DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 218 0x548, 0), 219 DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, 220 0x548, 1), 221 DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, 222 0x548, 2), 223 DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, 224 0x548, 3), 225 DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0, 226 0x548, 4), 227 DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK, 228 0x548, 5), 229 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, 230 0x550, 0), 231 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, 232 0x550, 1), 233 DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, 234 0x554, 0), 235 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, 236 0x554, 1), 237 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, 238 0x554, 2), 239 DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, 240 0x554, 3), 241 DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, 242 0x554, 4), 243 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, 244 0x554, 5), 245 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, 246 0x554, 6), 247 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, 248 0x554, 7), 249 DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, 250 0x558, 0), 251 DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, 252 0x558, 1), 253 DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 254 0x558, 2), 255 DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1, 256 0x568, 0), 257 DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2, 258 0x568, 1), 259 DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1, 260 0x568, 2), 261 DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2, 262 0x568, 3), 263 DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3, 264 0x568, 4), 265 DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4, 266 0x568, 5), 267 DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, 268 0x56c, 0), 269 DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, 270 0x56c, 0), 271 DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3, 272 0x56c, 1), 273 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 274 0x570, 0), 275 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, 276 0x570, 1), 277 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, 278 0x570, 2), 279 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, 280 0x570, 3), 281 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, 282 0x570, 4), 283 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, 284 0x570, 5), 285 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, 286 0x570, 6), 287 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, 288 0x570, 7), 289 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, 290 0x578, 0), 291 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, 292 0x578, 1), 293 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, 294 0x578, 2), 295 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, 296 0x578, 3), 297 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, 298 0x57c, 0), 299 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, 300 0x57c, 0), 301 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, 302 0x57c, 1), 303 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, 304 0x57c, 1), 305 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, 306 0x580, 0), 307 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, 308 0x580, 1), 309 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, 310 0x580, 2), 311 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, 312 0x580, 3), 313 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 314 0x584, 0), 315 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, 316 0x584, 1), 317 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, 318 0x584, 2), 319 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, 320 0x584, 3), 321 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, 322 0x584, 4), 323 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 324 0x588, 0), 325 DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, 326 0x588, 1), 327 DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, 328 0x590, 0), 329 DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, 330 0x590, 1), 331 DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, 332 0x590, 2), 333 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, 334 0x594, 0), 335 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, 336 0x598, 0), 337 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, 338 0x5a8, 0), 339 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, 340 0x5a8, 1), 341 DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, 342 0x5ac, 0), 343 }, 344 #ifdef CONFIG_CLK_R9A07G054 345 .drp = { 346 }, 347 #endif 348 }; 349 350 static struct rzg2l_reset r9a07g044_resets[] = { 351 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), 352 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), 353 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), 354 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), 355 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), 356 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), 357 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), 358 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), 359 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), 360 DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), 361 DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1), 362 DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2), 363 DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3), 364 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), 365 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), 366 DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), 367 DEF_RST(R9A07G044_SPI_RST, 0x850, 0), 368 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), 369 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), 370 DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), 371 DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), 372 DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), 373 DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0), 374 DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1), 375 DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2), 376 DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0), 377 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), 378 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), 379 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), 380 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3), 381 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0), 382 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1), 383 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2), 384 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3), 385 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0), 386 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1), 387 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0), 388 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1), 389 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2), 390 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3), 391 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0), 392 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1), 393 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2), 394 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), 395 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), 396 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), 397 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1), 398 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0), 399 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1), 400 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2), 401 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0), 402 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1), 403 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), 404 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), 405 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), 406 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0), 407 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1), 408 DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0), 409 }; 410 411 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 412 MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, 413 MOD_CLK_BASE + R9A07G044_IA55_CLK, 414 MOD_CLK_BASE + R9A07G044_DMAC_ACLK, 415 }; 416 417 #ifdef CONFIG_CLK_R9A07G044 418 const struct rzg2l_cpg_info r9a07g044_cpg_info = { 419 /* Core Clocks */ 420 .core_clks = core_clks.common, 421 .num_core_clks = ARRAY_SIZE(core_clks.common), 422 .last_dt_core_clk = LAST_DT_CORE_CLK, 423 .num_total_core_clks = MOD_CLK_BASE, 424 425 /* Critical Module Clocks */ 426 .crit_mod_clks = r9a07g044_crit_mod_clks, 427 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), 428 429 /* Module Clocks */ 430 .mod_clks = mod_clks.common, 431 .num_mod_clks = ARRAY_SIZE(mod_clks.common), 432 .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, 433 434 /* Resets */ 435 .resets = r9a07g044_resets, 436 .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ 437 438 .has_clk_mon_regs = true, 439 }; 440 #endif 441 442 #ifdef CONFIG_CLK_R9A07G054 443 const struct rzg2l_cpg_info r9a07g054_cpg_info = { 444 /* Core Clocks */ 445 .core_clks = core_clks.common, 446 .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp), 447 .last_dt_core_clk = LAST_DT_CORE_CLK, 448 .num_total_core_clks = MOD_CLK_BASE, 449 450 /* Critical Module Clocks */ 451 .crit_mod_clks = r9a07g044_crit_mod_clks, 452 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), 453 454 /* Module Clocks */ 455 .mod_clks = mod_clks.common, 456 .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp), 457 .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, 458 459 /* Resets */ 460 .resets = r9a07g044_resets, 461 .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ 462 463 .has_clk_mon_regs = true, 464 }; 465 #endif 466