1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/display/drm_scdc_helper.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_drv.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_simple_kms_helper.h>
40 #include <linux/clk.h>
41 #include <linux/component.h>
42 #include <linux/gpio/consumer.h>
43 #include <linux/i2c.h>
44 #include <linux/of_address.h>
45 #include <linux/of_platform.h>
46 #include <linux/pm_runtime.h>
47 #include <linux/rational.h>
48 #include <linux/reset.h>
49 #include <sound/dmaengine_pcm.h>
50 #include <sound/hdmi-codec.h>
51 #include <sound/pcm_drm_eld.h>
52 #include <sound/pcm_params.h>
53 #include <sound/soc.h>
54 #include "media/cec.h"
55 #include "vc4_drv.h"
56 #include "vc4_hdmi.h"
57 #include "vc4_hdmi_regs.h"
58 #include "vc4_regs.h"
59
60 #define VC5_HDMI_HORZA_HFP_SHIFT 16
61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62 #define VC5_HDMI_HORZA_VPOS BIT(15)
63 #define VC5_HDMI_HORZA_HPOS BIT(14)
64 #define VC5_HDMI_HORZA_HAP_SHIFT 0
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
66
67 #define VC5_HDMI_HORZB_HBP_SHIFT 16
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69 #define VC5_HDMI_HORZB_HSP_SHIFT 0
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
71
72 #define VC5_HDMI_VERTA_VSP_SHIFT 24
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74 #define VC5_HDMI_VERTA_VFP_SHIFT 16
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76 #define VC5_HDMI_VERTA_VAL_SHIFT 0
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
78
79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
81
82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
86
87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
88
89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
91
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
94
95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
96
97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
99
100 # define VC4_HD_M_SW_RST BIT(2)
101 # define VC4_HD_M_ENABLE BIT(0)
102
103 #define HSM_MIN_CLOCK_FREQ 120000000
104 #define CEC_CLOCK_FREQ 40000
105
106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
107
108 static const char * const output_format_str[] = {
109 [VC4_HDMI_OUTPUT_RGB] = "RGB",
110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
113 };
114
vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
116 {
117 if (fmt >= ARRAY_SIZE(output_format_str))
118 return "invalid";
119
120 return output_format_str[fmt];
121 }
122
123 static unsigned long long
124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
125 unsigned int bpc, enum vc4_hdmi_output_format fmt);
126
vc4_hdmi_supports_scrambling(struct drm_encoder * encoder)127 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder)
128 {
129 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
130 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
131
132 lockdep_assert_held(&vc4_hdmi->mutex);
133
134 if (!display->is_hdmi)
135 return false;
136
137 if (!display->hdmi.scdc.supported ||
138 !display->hdmi.scdc.scrambling.supported)
139 return false;
140
141 return true;
142 }
143
vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode * mode,unsigned int bpc,enum vc4_hdmi_output_format fmt)144 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
145 unsigned int bpc,
146 enum vc4_hdmi_output_format fmt)
147 {
148 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
149
150 return clock > HDMI_14_MAX_TMDS_CLK;
151 }
152
vc4_hdmi_is_full_range_rgb(struct vc4_hdmi * vc4_hdmi,const struct drm_display_mode * mode)153 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
154 const struct drm_display_mode *mode)
155 {
156 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
157
158 return !display->is_hdmi ||
159 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
160 }
161
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)162 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
163 {
164 struct drm_info_node *node = (struct drm_info_node *)m->private;
165 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
166 struct drm_device *drm = vc4_hdmi->connector.dev;
167 struct drm_printer p = drm_seq_file_printer(m);
168 int idx;
169
170 if (!drm_dev_enter(drm, &idx))
171 return -ENODEV;
172
173 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
174 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
175 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
176 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
177 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
178 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
179 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
180 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
181
182 drm_dev_exit(idx);
183
184 return 0;
185 }
186
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)187 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
188 {
189 struct drm_device *drm = vc4_hdmi->connector.dev;
190 unsigned long flags;
191 int idx;
192
193 /*
194 * We can be called by our bind callback, when the
195 * connector->dev pointer might not be initialised yet.
196 */
197 if (drm && !drm_dev_enter(drm, &idx))
198 return;
199
200 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
201
202 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
203 udelay(1);
204 HDMI_WRITE(HDMI_M_CTL, 0);
205
206 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
207
208 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
209 VC4_HDMI_SW_RESET_HDMI |
210 VC4_HDMI_SW_RESET_FORMAT_DETECT);
211
212 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
213
214 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
215
216 if (drm)
217 drm_dev_exit(idx);
218 }
219
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)220 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
221 {
222 struct drm_device *drm = vc4_hdmi->connector.dev;
223 unsigned long flags;
224 int idx;
225
226 /*
227 * We can be called by our bind callback, when the
228 * connector->dev pointer might not be initialised yet.
229 */
230 if (drm && !drm_dev_enter(drm, &idx))
231 return;
232
233 reset_control_reset(vc4_hdmi->reset);
234
235 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
236
237 HDMI_WRITE(HDMI_DVP_CTL, 0);
238
239 HDMI_WRITE(HDMI_CLOCK_STOP,
240 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
241
242 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
243
244 if (drm)
245 drm_dev_exit(idx);
246 }
247
248 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)249 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
250 {
251 struct drm_device *drm = vc4_hdmi->connector.dev;
252 unsigned long cec_rate;
253 unsigned long flags;
254 u16 clk_cnt;
255 u32 value;
256 int idx;
257
258 /*
259 * This function is called by our runtime_resume implementation
260 * and thus at bind time, when we haven't registered our
261 * connector yet and thus don't have a pointer to the DRM
262 * device.
263 */
264 if (drm && !drm_dev_enter(drm, &idx))
265 return;
266
267 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
268
269 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
270
271 value = HDMI_READ(HDMI_CEC_CNTRL_1);
272 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
273
274 /*
275 * Set the clock divider: the hsm_clock rate and this divider
276 * setting will give a 40 kHz CEC clock.
277 */
278 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
279 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
280 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
281
282 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
283
284 if (drm)
285 drm_dev_exit(idx);
286 }
287 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)288 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
289 #endif
290
reset_pipe(struct drm_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)291 static int reset_pipe(struct drm_crtc *crtc,
292 struct drm_modeset_acquire_ctx *ctx)
293 {
294 struct drm_atomic_state *state;
295 struct drm_crtc_state *crtc_state;
296 int ret;
297
298 state = drm_atomic_state_alloc(crtc->dev);
299 if (!state)
300 return -ENOMEM;
301
302 state->acquire_ctx = ctx;
303
304 crtc_state = drm_atomic_get_crtc_state(state, crtc);
305 if (IS_ERR(crtc_state)) {
306 ret = PTR_ERR(crtc_state);
307 goto out;
308 }
309
310 crtc_state->connectors_changed = true;
311
312 ret = drm_atomic_commit(state);
313 out:
314 drm_atomic_state_put(state);
315
316 return ret;
317 }
318
vc4_hdmi_reset_link(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx)319 static int vc4_hdmi_reset_link(struct drm_connector *connector,
320 struct drm_modeset_acquire_ctx *ctx)
321 {
322 struct drm_device *drm = connector->dev;
323 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
324 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
325 struct drm_connector_state *conn_state;
326 struct drm_crtc_state *crtc_state;
327 struct drm_crtc *crtc;
328 bool scrambling_needed;
329 u8 config;
330 int ret;
331
332 if (!connector)
333 return 0;
334
335 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
336 if (ret)
337 return ret;
338
339 conn_state = connector->state;
340 crtc = conn_state->crtc;
341 if (!crtc)
342 return 0;
343
344 ret = drm_modeset_lock(&crtc->mutex, ctx);
345 if (ret)
346 return ret;
347
348 crtc_state = crtc->state;
349 if (!crtc_state->active)
350 return 0;
351
352 mutex_lock(&vc4_hdmi->mutex);
353
354 if (!vc4_hdmi_supports_scrambling(encoder)) {
355 mutex_unlock(&vc4_hdmi->mutex);
356 return 0;
357 }
358
359 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
360 vc4_hdmi->output_bpc,
361 vc4_hdmi->output_format);
362 if (!scrambling_needed) {
363 mutex_unlock(&vc4_hdmi->mutex);
364 return 0;
365 }
366
367 if (conn_state->commit &&
368 !try_wait_for_completion(&conn_state->commit->hw_done)) {
369 mutex_unlock(&vc4_hdmi->mutex);
370 return 0;
371 }
372
373 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
374 if (ret < 0) {
375 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
376 mutex_unlock(&vc4_hdmi->mutex);
377 return 0;
378 }
379
380 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
381 mutex_unlock(&vc4_hdmi->mutex);
382 return 0;
383 }
384
385 mutex_unlock(&vc4_hdmi->mutex);
386
387 /*
388 * HDMI 2.0 says that one should not send scrambled data
389 * prior to configuring the sink scrambling, and that
390 * TMDS clock/data transmission should be suspended when
391 * changing the TMDS clock rate in the sink. So let's
392 * just do a full modeset here, even though some sinks
393 * would be perfectly happy if were to just reconfigure
394 * the SCDC settings on the fly.
395 */
396 return reset_pipe(crtc, ctx);
397 }
398
vc4_hdmi_handle_hotplug(struct vc4_hdmi * vc4_hdmi,struct drm_modeset_acquire_ctx * ctx,enum drm_connector_status status)399 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
400 struct drm_modeset_acquire_ctx *ctx,
401 enum drm_connector_status status)
402 {
403 struct drm_connector *connector = &vc4_hdmi->connector;
404 struct edid *edid;
405 int ret;
406
407 /*
408 * NOTE: This function should really be called with
409 * vc4_hdmi->mutex held, but doing so results in reentrancy
410 * issues since cec_s_phys_addr_from_edid might call
411 * .adap_enable, which leads to that funtion being called with
412 * our mutex held.
413 *
414 * A similar situation occurs with vc4_hdmi_reset_link() that
415 * will call into our KMS hooks if the scrambling was enabled.
416 *
417 * Concurrency isn't an issue at the moment since we don't share
418 * any state with any of the other frameworks so we can ignore
419 * the lock for now.
420 */
421
422 if (status == connector_status_disconnected) {
423 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
424 return;
425 }
426
427 edid = drm_get_edid(connector, vc4_hdmi->ddc);
428 if (!edid)
429 return;
430
431 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
432 kfree(edid);
433
434 for (;;) {
435 ret = vc4_hdmi_reset_link(connector, ctx);
436 if (ret == -EDEADLK) {
437 drm_modeset_backoff(ctx);
438 continue;
439 }
440
441 break;
442 }
443 }
444
vc4_hdmi_connector_detect_ctx(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)445 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
446 struct drm_modeset_acquire_ctx *ctx,
447 bool force)
448 {
449 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
450 enum drm_connector_status status = connector_status_disconnected;
451
452 /*
453 * NOTE: This function should really take vc4_hdmi->mutex, but
454 * doing so results in reentrancy issues since
455 * vc4_hdmi_handle_hotplug() can call into other functions that
456 * would take the mutex while it's held here.
457 *
458 * Concurrency isn't an issue at the moment since we don't share
459 * any state with any of the other frameworks so we can ignore
460 * the lock for now.
461 */
462
463 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
464
465 if (vc4_hdmi->hpd_gpio) {
466 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
467 status = connector_status_connected;
468 } else {
469 if (vc4_hdmi->variant->hp_detect &&
470 vc4_hdmi->variant->hp_detect(vc4_hdmi))
471 status = connector_status_connected;
472 }
473
474 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
475 pm_runtime_put(&vc4_hdmi->pdev->dev);
476
477 return status;
478 }
479
vc4_hdmi_connector_get_modes(struct drm_connector * connector)480 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
481 {
482 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
483 int ret = 0;
484 struct edid *edid;
485
486 /*
487 * NOTE: This function should really take vc4_hdmi->mutex, but
488 * doing so results in reentrancy issues since
489 * cec_s_phys_addr_from_edid might call .adap_enable, which
490 * leads to that funtion being called with our mutex held.
491 *
492 * Concurrency isn't an issue at the moment since we don't share
493 * any state with any of the other frameworks so we can ignore
494 * the lock for now.
495 */
496
497 edid = drm_get_edid(connector, vc4_hdmi->ddc);
498 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
499 if (!edid)
500 return -ENODEV;
501
502 drm_connector_update_edid_property(connector, edid);
503 ret = drm_add_edid_modes(connector, edid);
504 kfree(edid);
505
506 if (vc4_hdmi->disable_4kp60) {
507 struct drm_device *drm = connector->dev;
508 const struct drm_display_mode *mode;
509
510 list_for_each_entry(mode, &connector->probed_modes, head) {
511 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
512 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
513 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
514 }
515 }
516 }
517
518 return ret;
519 }
520
vc4_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)521 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
522 struct drm_atomic_state *state)
523 {
524 struct drm_connector_state *old_state =
525 drm_atomic_get_old_connector_state(state, connector);
526 struct drm_connector_state *new_state =
527 drm_atomic_get_new_connector_state(state, connector);
528 struct drm_crtc *crtc = new_state->crtc;
529
530 if (!crtc)
531 return 0;
532
533 if (old_state->colorspace != new_state->colorspace ||
534 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
535 struct drm_crtc_state *crtc_state;
536
537 crtc_state = drm_atomic_get_crtc_state(state, crtc);
538 if (IS_ERR(crtc_state))
539 return PTR_ERR(crtc_state);
540
541 crtc_state->mode_changed = true;
542 }
543
544 return 0;
545 }
546
vc4_hdmi_connector_reset(struct drm_connector * connector)547 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
548 {
549 struct vc4_hdmi_connector_state *old_state =
550 conn_state_to_vc4_hdmi_conn_state(connector->state);
551 struct vc4_hdmi_connector_state *new_state =
552 kzalloc(sizeof(*new_state), GFP_KERNEL);
553
554 if (connector->state)
555 __drm_atomic_helper_connector_destroy_state(connector->state);
556
557 kfree(old_state);
558 __drm_atomic_helper_connector_reset(connector, &new_state->base);
559
560 if (!new_state)
561 return;
562
563 new_state->base.max_bpc = 8;
564 new_state->base.max_requested_bpc = 8;
565 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
566 drm_atomic_helper_connector_tv_reset(connector);
567 }
568
569 static struct drm_connector_state *
vc4_hdmi_connector_duplicate_state(struct drm_connector * connector)570 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
571 {
572 struct drm_connector_state *conn_state = connector->state;
573 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
574 struct vc4_hdmi_connector_state *new_state;
575
576 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
577 if (!new_state)
578 return NULL;
579
580 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
581 new_state->output_bpc = vc4_state->output_bpc;
582 new_state->output_format = vc4_state->output_format;
583 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
584
585 return &new_state->base;
586 }
587
588 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
589 .fill_modes = drm_helper_probe_single_connector_modes,
590 .reset = vc4_hdmi_connector_reset,
591 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
592 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
593 };
594
595 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
596 .detect_ctx = vc4_hdmi_connector_detect_ctx,
597 .get_modes = vc4_hdmi_connector_get_modes,
598 .atomic_check = vc4_hdmi_connector_atomic_check,
599 };
600
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)601 static int vc4_hdmi_connector_init(struct drm_device *dev,
602 struct vc4_hdmi *vc4_hdmi)
603 {
604 struct drm_connector *connector = &vc4_hdmi->connector;
605 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
606 int ret;
607
608 ret = drmm_connector_init(dev, connector,
609 &vc4_hdmi_connector_funcs,
610 DRM_MODE_CONNECTOR_HDMIA,
611 vc4_hdmi->ddc);
612 if (ret)
613 return ret;
614
615 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
616
617 /*
618 * Some of the properties below require access to state, like bpc.
619 * Allocate some default initial connector state with our reset helper.
620 */
621 if (connector->funcs->reset)
622 connector->funcs->reset(connector);
623
624 /* Create and attach TV margin props to this connector. */
625 ret = drm_mode_create_tv_margin_properties(dev);
626 if (ret)
627 return ret;
628
629 ret = drm_mode_create_hdmi_colorspace_property(connector);
630 if (ret)
631 return ret;
632
633 drm_connector_attach_colorspace_property(connector);
634 drm_connector_attach_tv_margin_properties(connector);
635 drm_connector_attach_max_bpc_property(connector, 8, 12);
636
637 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
638 DRM_CONNECTOR_POLL_DISCONNECT);
639
640 connector->interlace_allowed = 1;
641 connector->doublescan_allowed = 0;
642 connector->stereo_allowed = 1;
643
644 if (vc4_hdmi->variant->supports_hdr)
645 drm_connector_attach_hdr_output_metadata_property(connector);
646
647 drm_connector_attach_encoder(connector, encoder);
648
649 return 0;
650 }
651
vc4_hdmi_stop_packet(struct drm_encoder * encoder,enum hdmi_infoframe_type type,bool poll)652 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
653 enum hdmi_infoframe_type type,
654 bool poll)
655 {
656 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
657 struct drm_device *drm = vc4_hdmi->connector.dev;
658 u32 packet_id = type - 0x80;
659 unsigned long flags;
660 int ret = 0;
661 int idx;
662
663 if (!drm_dev_enter(drm, &idx))
664 return -ENODEV;
665
666 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
667 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
668 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
669 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
670
671 if (poll) {
672 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
673 BIT(packet_id)), 100);
674 }
675
676 drm_dev_exit(idx);
677 return ret;
678 }
679
vc4_hdmi_write_infoframe(struct drm_encoder * encoder,union hdmi_infoframe * frame)680 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
681 union hdmi_infoframe *frame)
682 {
683 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
684 struct drm_device *drm = vc4_hdmi->connector.dev;
685 u32 packet_id = frame->any.type - 0x80;
686 const struct vc4_hdmi_register *ram_packet_start =
687 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
688 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
689 u32 packet_reg_next = ram_packet_start->offset +
690 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
691 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
692 ram_packet_start->reg);
693 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
694 unsigned long flags;
695 ssize_t len, i;
696 int ret;
697 int idx;
698
699 if (!drm_dev_enter(drm, &idx))
700 return;
701
702 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
703 VC4_HDMI_RAM_PACKET_ENABLE),
704 "Packet RAM has to be on to store the packet.");
705
706 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
707 if (len < 0)
708 goto out;
709
710 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
711 if (ret) {
712 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
713 goto out;
714 }
715
716 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
717
718 for (i = 0; i < len; i += 7) {
719 writel(buffer[i + 0] << 0 |
720 buffer[i + 1] << 8 |
721 buffer[i + 2] << 16,
722 base + packet_reg);
723 packet_reg += 4;
724
725 writel(buffer[i + 3] << 0 |
726 buffer[i + 4] << 8 |
727 buffer[i + 5] << 16 |
728 buffer[i + 6] << 24,
729 base + packet_reg);
730 packet_reg += 4;
731 }
732
733 /*
734 * clear remainder of packet ram as it's included in the
735 * infoframe and triggers a checksum error on hdmi analyser
736 */
737 for (; packet_reg < packet_reg_next; packet_reg += 4)
738 writel(0, base + packet_reg);
739
740 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
741 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
742
743 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
744
745 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
746 BIT(packet_id)), 100);
747 if (ret)
748 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
749
750 out:
751 drm_dev_exit(idx);
752 }
753
vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe * frame,enum vc4_hdmi_output_format fmt)754 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
755 enum vc4_hdmi_output_format fmt)
756 {
757 switch (fmt) {
758 case VC4_HDMI_OUTPUT_RGB:
759 frame->colorspace = HDMI_COLORSPACE_RGB;
760 break;
761
762 case VC4_HDMI_OUTPUT_YUV420:
763 frame->colorspace = HDMI_COLORSPACE_YUV420;
764 break;
765
766 case VC4_HDMI_OUTPUT_YUV422:
767 frame->colorspace = HDMI_COLORSPACE_YUV422;
768 break;
769
770 case VC4_HDMI_OUTPUT_YUV444:
771 frame->colorspace = HDMI_COLORSPACE_YUV444;
772 break;
773
774 default:
775 break;
776 }
777 }
778
vc4_hdmi_set_avi_infoframe(struct drm_encoder * encoder)779 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
780 {
781 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
782 struct drm_connector *connector = &vc4_hdmi->connector;
783 struct drm_connector_state *cstate = connector->state;
784 struct vc4_hdmi_connector_state *vc4_state =
785 conn_state_to_vc4_hdmi_conn_state(cstate);
786 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
787 union hdmi_infoframe frame;
788 int ret;
789
790 lockdep_assert_held(&vc4_hdmi->mutex);
791
792 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
793 connector, mode);
794 if (ret < 0) {
795 DRM_ERROR("couldn't fill AVI infoframe\n");
796 return;
797 }
798
799 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
800 connector, mode,
801 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
802 HDMI_QUANTIZATION_RANGE_FULL :
803 HDMI_QUANTIZATION_RANGE_LIMITED);
804 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
805 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
806 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
807
808 vc4_hdmi_write_infoframe(encoder, &frame);
809 }
810
vc4_hdmi_set_spd_infoframe(struct drm_encoder * encoder)811 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
812 {
813 union hdmi_infoframe frame;
814 int ret;
815
816 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
817 if (ret < 0) {
818 DRM_ERROR("couldn't fill SPD infoframe\n");
819 return;
820 }
821
822 frame.spd.sdi = HDMI_SPD_SDI_PC;
823
824 vc4_hdmi_write_infoframe(encoder, &frame);
825 }
826
vc4_hdmi_set_audio_infoframe(struct drm_encoder * encoder)827 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
828 {
829 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
830 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
831 union hdmi_infoframe frame;
832
833 memcpy(&frame.audio, audio, sizeof(*audio));
834
835 if (vc4_hdmi->packet_ram_enabled)
836 vc4_hdmi_write_infoframe(encoder, &frame);
837 }
838
vc4_hdmi_set_hdr_infoframe(struct drm_encoder * encoder)839 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
840 {
841 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
842 struct drm_connector *connector = &vc4_hdmi->connector;
843 struct drm_connector_state *conn_state = connector->state;
844 union hdmi_infoframe frame;
845
846 lockdep_assert_held(&vc4_hdmi->mutex);
847
848 if (!vc4_hdmi->variant->supports_hdr)
849 return;
850
851 if (!conn_state->hdr_output_metadata)
852 return;
853
854 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
855 return;
856
857 vc4_hdmi_write_infoframe(encoder, &frame);
858 }
859
vc4_hdmi_set_infoframes(struct drm_encoder * encoder)860 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
861 {
862 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
863
864 lockdep_assert_held(&vc4_hdmi->mutex);
865
866 vc4_hdmi_set_avi_infoframe(encoder);
867 vc4_hdmi_set_spd_infoframe(encoder);
868 /*
869 * If audio was streaming, then we need to reenabled the audio
870 * infoframe here during encoder_enable.
871 */
872 if (vc4_hdmi->audio.streaming)
873 vc4_hdmi_set_audio_infoframe(encoder);
874
875 vc4_hdmi_set_hdr_infoframe(encoder);
876 }
877
878 #define SCRAMBLING_POLLING_DELAY_MS 1000
879
vc4_hdmi_enable_scrambling(struct drm_encoder * encoder)880 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
881 {
882 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
883 struct drm_device *drm = vc4_hdmi->connector.dev;
884 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
885 unsigned long flags;
886 int idx;
887
888 lockdep_assert_held(&vc4_hdmi->mutex);
889
890 if (!vc4_hdmi_supports_scrambling(encoder))
891 return;
892
893 if (!vc4_hdmi_mode_needs_scrambling(mode,
894 vc4_hdmi->output_bpc,
895 vc4_hdmi->output_format))
896 return;
897
898 if (!drm_dev_enter(drm, &idx))
899 return;
900
901 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
902 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
903
904 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
905 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
906 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
907 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
908
909 drm_dev_exit(idx);
910
911 vc4_hdmi->scdc_enabled = true;
912
913 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
914 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
915 }
916
vc4_hdmi_disable_scrambling(struct drm_encoder * encoder)917 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
918 {
919 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
920 struct drm_device *drm = vc4_hdmi->connector.dev;
921 unsigned long flags;
922 int idx;
923
924 lockdep_assert_held(&vc4_hdmi->mutex);
925
926 if (!vc4_hdmi->scdc_enabled)
927 return;
928
929 vc4_hdmi->scdc_enabled = false;
930
931 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
932 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
933
934 if (!drm_dev_enter(drm, &idx))
935 return;
936
937 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
938 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
939 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
940 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
941
942 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
943 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
944
945 drm_dev_exit(idx);
946 }
947
vc4_hdmi_scrambling_wq(struct work_struct * work)948 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
949 {
950 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
951 struct vc4_hdmi,
952 scrambling_work);
953
954 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
955 return;
956
957 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
958 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
959
960 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
961 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
962 }
963
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)964 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
965 struct drm_atomic_state *state)
966 {
967 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
968 struct drm_device *drm = vc4_hdmi->connector.dev;
969 unsigned long flags;
970 int idx;
971
972 mutex_lock(&vc4_hdmi->mutex);
973
974 vc4_hdmi->packet_ram_enabled = false;
975
976 if (!drm_dev_enter(drm, &idx))
977 goto out;
978
979 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
980
981 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
982
983 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
984
985 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
986
987 mdelay(1);
988
989 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
990 HDMI_WRITE(HDMI_VID_CTL,
991 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
992 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
993
994 vc4_hdmi_disable_scrambling(encoder);
995
996 drm_dev_exit(idx);
997
998 out:
999 mutex_unlock(&vc4_hdmi->mutex);
1000 }
1001
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder,struct drm_atomic_state * state)1002 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1003 struct drm_atomic_state *state)
1004 {
1005 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1006 struct drm_device *drm = vc4_hdmi->connector.dev;
1007 unsigned long flags;
1008 int ret;
1009 int idx;
1010
1011 mutex_lock(&vc4_hdmi->mutex);
1012
1013 if (!drm_dev_enter(drm, &idx))
1014 goto out;
1015
1016 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1017 HDMI_WRITE(HDMI_VID_CTL,
1018 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1019 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1020
1021 if (vc4_hdmi->variant->phy_disable)
1022 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1023
1024 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1025 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1026
1027 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1028 if (ret < 0)
1029 DRM_ERROR("Failed to release power domain: %d\n", ret);
1030
1031 drm_dev_exit(idx);
1032
1033 out:
1034 mutex_unlock(&vc4_hdmi->mutex);
1035 }
1036
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1037 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1038 struct drm_connector_state *state,
1039 const struct drm_display_mode *mode)
1040 {
1041 struct drm_device *drm = vc4_hdmi->connector.dev;
1042 unsigned long flags;
1043 u32 csc_ctl;
1044 int idx;
1045
1046 if (!drm_dev_enter(drm, &idx))
1047 return;
1048
1049 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1050
1051 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1052 VC4_HD_CSC_CTL_ORDER);
1053
1054 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
1055 /* CEA VICs other than #1 requre limited range RGB
1056 * output unless overridden by an AVI infoframe.
1057 * Apply a colorspace conversion to squash 0-255 down
1058 * to 16-235. The matrix here is:
1059 *
1060 * [ 0 0 0.8594 16]
1061 * [ 0 0.8594 0 16]
1062 * [ 0.8594 0 0 16]
1063 * [ 0 0 0 1]
1064 */
1065 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1066 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1067 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1068 VC4_HD_CSC_CTL_MODE);
1069
1070 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1071 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1072 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1073 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1074 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1075 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1076 }
1077
1078 /* The RGB order applies even when CSC is disabled. */
1079 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1080
1081 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1082
1083 drm_dev_exit(idx);
1084 }
1085
1086 /*
1087 * If we need to output Full Range RGB, then use the unity matrix
1088 *
1089 * [ 1 0 0 0]
1090 * [ 0 1 0 0]
1091 * [ 0 0 1 0]
1092 *
1093 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1094 */
1095 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
1096 { 0x2000, 0x0000, 0x0000, 0x0000 },
1097 { 0x0000, 0x2000, 0x0000, 0x0000 },
1098 { 0x0000, 0x0000, 0x2000, 0x0000 },
1099 };
1100
1101 /*
1102 * CEA VICs other than #1 require limited range RGB output unless
1103 * overridden by an AVI infoframe. Apply a colorspace conversion to
1104 * squash 0-255 down to 16-235. The matrix here is:
1105 *
1106 * [ 0.8594 0 0 16]
1107 * [ 0 0.8594 0 16]
1108 * [ 0 0 0.8594 16]
1109 *
1110 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1111 */
1112 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
1113 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1114 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1115 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1116 };
1117
1118 /*
1119 * Conversion between Full Range RGB and Full Range YUV422 using the
1120 * BT.709 Colorspace
1121 *
1122 *
1123 * [ 0.181906 0.611804 0.061758 16 ]
1124 * [ -0.100268 -0.337232 0.437500 128 ]
1125 * [ 0.437500 -0.397386 -0.040114 128 ]
1126 *
1127 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1128 */
1129 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
1130 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1131 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1132 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1133 };
1134
1135 /*
1136 * Conversion between Full Range RGB and Full Range YUV444 using the
1137 * BT.709 Colorspace
1138 *
1139 * [ -0.100268 -0.337232 0.437500 128 ]
1140 * [ 0.437500 -0.397386 -0.040114 128 ]
1141 * [ 0.181906 0.611804 0.061758 16 ]
1142 *
1143 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1144 */
1145 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
1146 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1147 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1148 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1149 };
1150
vc5_hdmi_set_csc_coeffs(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1151 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1152 const u16 coeffs[3][4])
1153 {
1154 lockdep_assert_held(&vc4_hdmi->hw_lock);
1155
1156 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1157 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1158 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1159 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1160 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1161 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1162 }
1163
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1164 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1165 struct drm_connector_state *state,
1166 const struct drm_display_mode *mode)
1167 {
1168 struct drm_device *drm = vc4_hdmi->connector.dev;
1169 struct vc4_hdmi_connector_state *vc4_state =
1170 conn_state_to_vc4_hdmi_conn_state(state);
1171 unsigned long flags;
1172 u32 if_cfg = 0;
1173 u32 if_xbar = 0x543210;
1174 u32 csc_chan_ctl = 0;
1175 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1176 VC5_MT_CP_CSC_CTL_MODE);
1177 int idx;
1178
1179 if (!drm_dev_enter(drm, &idx))
1180 return;
1181
1182 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1183
1184 switch (vc4_state->output_format) {
1185 case VC4_HDMI_OUTPUT_YUV444:
1186 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1187 break;
1188
1189 case VC4_HDMI_OUTPUT_YUV422:
1190 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1191 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1192 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1193 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1194
1195 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1196 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1197
1198 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1199 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1200
1201 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1202 break;
1203
1204 case VC4_HDMI_OUTPUT_RGB:
1205 if_xbar = 0x354021;
1206
1207 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1208 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1209 else
1210 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1211 break;
1212
1213 default:
1214 break;
1215 }
1216
1217 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1218 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1219 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1220 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1221
1222 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1223
1224 drm_dev_exit(idx);
1225 }
1226
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1227 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1228 struct drm_connector_state *state,
1229 const struct drm_display_mode *mode)
1230 {
1231 struct drm_device *drm = vc4_hdmi->connector.dev;
1232 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1233 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1234 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1235 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1236 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1237 VC4_HDMI_VERTA_VSP) |
1238 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1239 VC4_HDMI_VERTA_VFP) |
1240 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1241 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1242 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1243 interlaced,
1244 VC4_HDMI_VERTB_VBP));
1245 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1246 VC4_SET_FIELD(mode->crtc_vtotal -
1247 mode->crtc_vsync_end,
1248 VC4_HDMI_VERTB_VBP));
1249 unsigned long flags;
1250 u32 reg;
1251 int idx;
1252
1253 if (!drm_dev_enter(drm, &idx))
1254 return;
1255
1256 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1257
1258 HDMI_WRITE(HDMI_HORZA,
1259 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1260 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1261 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1262 VC4_HDMI_HORZA_HAP));
1263
1264 HDMI_WRITE(HDMI_HORZB,
1265 VC4_SET_FIELD((mode->htotal -
1266 mode->hsync_end) * pixel_rep,
1267 VC4_HDMI_HORZB_HBP) |
1268 VC4_SET_FIELD((mode->hsync_end -
1269 mode->hsync_start) * pixel_rep,
1270 VC4_HDMI_HORZB_HSP) |
1271 VC4_SET_FIELD((mode->hsync_start -
1272 mode->hdisplay) * pixel_rep,
1273 VC4_HDMI_HORZB_HFP));
1274
1275 HDMI_WRITE(HDMI_VERTA0, verta);
1276 HDMI_WRITE(HDMI_VERTA1, verta);
1277
1278 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1279 HDMI_WRITE(HDMI_VERTB1, vertb);
1280
1281 reg = HDMI_READ(HDMI_MISC_CONTROL);
1282 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1283 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1284 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1285
1286 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1287
1288 drm_dev_exit(idx);
1289 }
1290
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1291 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1292 struct drm_connector_state *state,
1293 const struct drm_display_mode *mode)
1294 {
1295 struct drm_device *drm = vc4_hdmi->connector.dev;
1296 const struct vc4_hdmi_connector_state *vc4_state =
1297 conn_state_to_vc4_hdmi_conn_state(state);
1298 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1299 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1300 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1301 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1302 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1303 VC5_HDMI_VERTA_VSP) |
1304 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1305 VC5_HDMI_VERTA_VFP) |
1306 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1307 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1308 VC5_HDMI_VERTB_VSPO) |
1309 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1310 interlaced,
1311 VC4_HDMI_VERTB_VBP));
1312 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1313 VC4_SET_FIELD(mode->crtc_vtotal -
1314 mode->crtc_vsync_end,
1315 VC4_HDMI_VERTB_VBP));
1316 unsigned long flags;
1317 unsigned char gcp;
1318 bool gcp_en;
1319 u32 reg;
1320 int idx;
1321
1322 if (!drm_dev_enter(drm, &idx))
1323 return;
1324
1325 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1326
1327 HDMI_WRITE(HDMI_HORZA,
1328 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1329 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1330 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1331 VC5_HDMI_HORZA_HAP) |
1332 VC4_SET_FIELD((mode->hsync_start -
1333 mode->hdisplay) * pixel_rep,
1334 VC5_HDMI_HORZA_HFP));
1335
1336 HDMI_WRITE(HDMI_HORZB,
1337 VC4_SET_FIELD((mode->htotal -
1338 mode->hsync_end) * pixel_rep,
1339 VC5_HDMI_HORZB_HBP) |
1340 VC4_SET_FIELD((mode->hsync_end -
1341 mode->hsync_start) * pixel_rep,
1342 VC5_HDMI_HORZB_HSP));
1343
1344 HDMI_WRITE(HDMI_VERTA0, verta);
1345 HDMI_WRITE(HDMI_VERTA1, verta);
1346
1347 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1348 HDMI_WRITE(HDMI_VERTB1, vertb);
1349
1350 switch (vc4_state->output_bpc) {
1351 case 12:
1352 gcp = 6;
1353 gcp_en = true;
1354 break;
1355 case 10:
1356 gcp = 5;
1357 gcp_en = true;
1358 break;
1359 case 8:
1360 default:
1361 gcp = 4;
1362 gcp_en = false;
1363 break;
1364 }
1365
1366 /*
1367 * YCC422 is always 36-bit and not considered deep colour so
1368 * doesn't signal in GCP.
1369 */
1370 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1371 gcp = 4;
1372 gcp_en = false;
1373 }
1374
1375 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1376 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1377 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1378 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1379 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1380 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1381
1382 reg = HDMI_READ(HDMI_GCP_WORD_1);
1383 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1384 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1385 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1386
1387 reg = HDMI_READ(HDMI_GCP_CONFIG);
1388 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1389 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1390 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1391
1392 reg = HDMI_READ(HDMI_MISC_CONTROL);
1393 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1394 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1395 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1396
1397 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1398
1399 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1400
1401 drm_dev_exit(idx);
1402 }
1403
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)1404 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1405 {
1406 struct drm_device *drm = vc4_hdmi->connector.dev;
1407 unsigned long flags;
1408 u32 drift;
1409 int ret;
1410 int idx;
1411
1412 if (!drm_dev_enter(drm, &idx))
1413 return;
1414
1415 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1416
1417 drift = HDMI_READ(HDMI_FIFO_CTL);
1418 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1419
1420 HDMI_WRITE(HDMI_FIFO_CTL,
1421 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1422 HDMI_WRITE(HDMI_FIFO_CTL,
1423 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1424
1425 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1426
1427 usleep_range(1000, 1100);
1428
1429 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1430
1431 HDMI_WRITE(HDMI_FIFO_CTL,
1432 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1433 HDMI_WRITE(HDMI_FIFO_CTL,
1434 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1435
1436 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1437
1438 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1439 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1440 WARN_ONCE(ret, "Timeout waiting for "
1441 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1442
1443 drm_dev_exit(idx);
1444 }
1445
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder,struct drm_atomic_state * state)1446 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1447 struct drm_atomic_state *state)
1448 {
1449 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1450 struct drm_device *drm = vc4_hdmi->connector.dev;
1451 struct drm_connector *connector = &vc4_hdmi->connector;
1452 struct drm_connector_state *conn_state =
1453 drm_atomic_get_new_connector_state(state, connector);
1454 struct vc4_hdmi_connector_state *vc4_conn_state =
1455 conn_state_to_vc4_hdmi_conn_state(conn_state);
1456 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1457 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1458 unsigned long bvb_rate, hsm_rate;
1459 unsigned long flags;
1460 int ret;
1461 int idx;
1462
1463 mutex_lock(&vc4_hdmi->mutex);
1464
1465 if (!drm_dev_enter(drm, &idx))
1466 goto out;
1467
1468 /*
1469 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1470 * be faster than pixel clock, infinitesimally faster, tested in
1471 * simulation. Otherwise, exact value is unimportant for HDMI
1472 * operation." This conflicts with bcm2835's vc4 documentation, which
1473 * states HSM's clock has to be at least 108% of the pixel clock.
1474 *
1475 * Real life tests reveal that vc4's firmware statement holds up, and
1476 * users are able to use pixel clocks closer to HSM's, namely for
1477 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1478 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1479 * 162MHz.
1480 *
1481 * Additionally, the AXI clock needs to be at least 25% of
1482 * pixel clock, but HSM ends up being the limiting factor.
1483 */
1484 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1485 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1486 if (ret) {
1487 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1488 goto err_dev_exit;
1489 }
1490
1491 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1492 if (ret < 0) {
1493 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1494 goto err_dev_exit;
1495 }
1496
1497 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1498 if (ret) {
1499 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1500 goto err_put_runtime_pm;
1501 }
1502
1503 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1504 if (ret) {
1505 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1506 goto err_put_runtime_pm;
1507 }
1508
1509
1510 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1511
1512 if (tmds_char_rate > 297000000)
1513 bvb_rate = 300000000;
1514 else if (tmds_char_rate > 148500000)
1515 bvb_rate = 150000000;
1516 else
1517 bvb_rate = 75000000;
1518
1519 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1520 if (ret) {
1521 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1522 goto err_disable_pixel_clock;
1523 }
1524
1525 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1526 if (ret) {
1527 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1528 goto err_disable_pixel_clock;
1529 }
1530
1531 if (vc4_hdmi->variant->phy_init)
1532 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1533
1534 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1535
1536 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1537 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1538 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1539 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1540
1541 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1542
1543 if (vc4_hdmi->variant->set_timings)
1544 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1545
1546 drm_dev_exit(idx);
1547
1548 mutex_unlock(&vc4_hdmi->mutex);
1549
1550 return;
1551
1552 err_disable_pixel_clock:
1553 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1554 err_put_runtime_pm:
1555 pm_runtime_put(&vc4_hdmi->pdev->dev);
1556 err_dev_exit:
1557 drm_dev_exit(idx);
1558 out:
1559 mutex_unlock(&vc4_hdmi->mutex);
1560 return;
1561 }
1562
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1563 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1564 struct drm_atomic_state *state)
1565 {
1566 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1567 struct drm_device *drm = vc4_hdmi->connector.dev;
1568 struct drm_connector *connector = &vc4_hdmi->connector;
1569 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1570 struct drm_connector_state *conn_state =
1571 drm_atomic_get_new_connector_state(state, connector);
1572 unsigned long flags;
1573 int idx;
1574
1575 mutex_lock(&vc4_hdmi->mutex);
1576
1577 if (!drm_dev_enter(drm, &idx))
1578 goto out;
1579
1580 if (vc4_hdmi->variant->csc_setup)
1581 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1582
1583 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1584 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1585 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1586
1587 drm_dev_exit(idx);
1588
1589 out:
1590 mutex_unlock(&vc4_hdmi->mutex);
1591 }
1592
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1593 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1594 struct drm_atomic_state *state)
1595 {
1596 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1597 struct drm_device *drm = vc4_hdmi->connector.dev;
1598 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1599 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1600 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1601 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1602 unsigned long flags;
1603 int ret;
1604 int idx;
1605
1606 mutex_lock(&vc4_hdmi->mutex);
1607
1608 if (!drm_dev_enter(drm, &idx))
1609 goto out;
1610
1611 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1612
1613 HDMI_WRITE(HDMI_VID_CTL,
1614 VC4_HD_VID_CTL_ENABLE |
1615 VC4_HD_VID_CTL_CLRRGB |
1616 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1617 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1618 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1619 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1620
1621 HDMI_WRITE(HDMI_VID_CTL,
1622 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1623
1624 if (display->is_hdmi) {
1625 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1626 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1627 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1628
1629 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1630
1631 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1632 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1633 WARN_ONCE(ret, "Timeout waiting for "
1634 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1635 } else {
1636 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1637 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1638 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1639 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1640 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1641 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1642
1643 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1644
1645 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1646 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1647 WARN_ONCE(ret, "Timeout waiting for "
1648 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1649 }
1650
1651 if (display->is_hdmi) {
1652 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1653
1654 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1655 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1656
1657 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1658 VC4_HDMI_RAM_PACKET_ENABLE);
1659
1660 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1661 vc4_hdmi->packet_ram_enabled = true;
1662
1663 vc4_hdmi_set_infoframes(encoder);
1664 }
1665
1666 vc4_hdmi_recenter_fifo(vc4_hdmi);
1667 vc4_hdmi_enable_scrambling(encoder);
1668
1669 drm_dev_exit(idx);
1670
1671 out:
1672 mutex_unlock(&vc4_hdmi->mutex);
1673 }
1674
vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1675 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1676 struct drm_crtc_state *crtc_state,
1677 struct drm_connector_state *conn_state)
1678 {
1679 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1680 struct vc4_hdmi_connector_state *vc4_state =
1681 conn_state_to_vc4_hdmi_conn_state(conn_state);
1682
1683 mutex_lock(&vc4_hdmi->mutex);
1684 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1685 &crtc_state->adjusted_mode);
1686 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1687 vc4_hdmi->output_format = vc4_state->output_format;
1688 mutex_unlock(&vc4_hdmi->mutex);
1689 }
1690
1691 static bool
vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi * vc4_hdmi,const struct drm_display_info * info,const struct drm_display_mode * mode,unsigned int format,unsigned int bpc)1692 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1693 const struct drm_display_info *info,
1694 const struct drm_display_mode *mode,
1695 unsigned int format, unsigned int bpc)
1696 {
1697 struct drm_device *dev = vc4_hdmi->connector.dev;
1698 u8 vic = drm_match_cea_mode(mode);
1699
1700 if (vic == 1 && bpc != 8) {
1701 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1702 return false;
1703 }
1704
1705 if (!info->is_hdmi &&
1706 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1707 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1708 return false;
1709 }
1710
1711 switch (format) {
1712 case VC4_HDMI_OUTPUT_RGB:
1713 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1714
1715 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1716 return false;
1717
1718 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1719 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1720 return false;
1721 }
1722
1723 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1724 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1725 return false;
1726 }
1727
1728 drm_dbg(dev, "RGB format supported in that configuration.\n");
1729
1730 return true;
1731
1732 case VC4_HDMI_OUTPUT_YUV422:
1733 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1734
1735 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1736 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1737 return false;
1738 }
1739
1740 if (bpc != 12) {
1741 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1742 return false;
1743 }
1744
1745 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1746
1747 return true;
1748
1749 case VC4_HDMI_OUTPUT_YUV444:
1750 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1751
1752 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1753 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1754 return false;
1755 }
1756
1757 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1758 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1759 return false;
1760 }
1761
1762 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1763 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1764 return false;
1765 }
1766
1767 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1768
1769 return true;
1770 }
1771
1772 return false;
1773 }
1774
1775 static enum drm_mode_status
vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi * vc4_hdmi,unsigned long long clock)1776 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1777 unsigned long long clock)
1778 {
1779 const struct drm_connector *connector = &vc4_hdmi->connector;
1780 const struct drm_display_info *info = &connector->display_info;
1781
1782 if (clock > vc4_hdmi->variant->max_pixel_clock)
1783 return MODE_CLOCK_HIGH;
1784
1785 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
1786 return MODE_CLOCK_HIGH;
1787
1788 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1789 return MODE_CLOCK_HIGH;
1790
1791 return MODE_OK;
1792 }
1793
1794 static unsigned long long
vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode * mode,unsigned int bpc,enum vc4_hdmi_output_format fmt)1795 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1796 unsigned int bpc,
1797 enum vc4_hdmi_output_format fmt)
1798 {
1799 unsigned long long clock = mode->clock * 1000ULL;
1800
1801 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1802 clock = clock * 2;
1803
1804 if (fmt == VC4_HDMI_OUTPUT_YUV422)
1805 bpc = 8;
1806
1807 clock = clock * bpc;
1808 do_div(clock, 8);
1809
1810 return clock;
1811 }
1812
1813 static int
vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi * vc4_hdmi,struct vc4_hdmi_connector_state * vc4_state,const struct drm_display_mode * mode,unsigned int bpc,unsigned int fmt)1814 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1815 struct vc4_hdmi_connector_state *vc4_state,
1816 const struct drm_display_mode *mode,
1817 unsigned int bpc, unsigned int fmt)
1818 {
1819 unsigned long long clock;
1820
1821 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1822 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1823 return -EINVAL;
1824
1825 vc4_state->tmds_char_rate = clock;
1826
1827 return 0;
1828 }
1829
1830 static int
vc4_hdmi_encoder_compute_format(const struct vc4_hdmi * vc4_hdmi,struct vc4_hdmi_connector_state * vc4_state,const struct drm_display_mode * mode,unsigned int bpc)1831 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1832 struct vc4_hdmi_connector_state *vc4_state,
1833 const struct drm_display_mode *mode,
1834 unsigned int bpc)
1835 {
1836 struct drm_device *dev = vc4_hdmi->connector.dev;
1837 const struct drm_connector *connector = &vc4_hdmi->connector;
1838 const struct drm_display_info *info = &connector->display_info;
1839 unsigned int format;
1840
1841 drm_dbg(dev, "Trying with an RGB output\n");
1842
1843 format = VC4_HDMI_OUTPUT_RGB;
1844 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1845 int ret;
1846
1847 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1848 mode, bpc, format);
1849 if (!ret) {
1850 vc4_state->output_format = format;
1851 return 0;
1852 }
1853 }
1854
1855 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1856
1857 format = VC4_HDMI_OUTPUT_YUV422;
1858 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1859 int ret;
1860
1861 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1862 mode, bpc, format);
1863 if (!ret) {
1864 vc4_state->output_format = format;
1865 return 0;
1866 }
1867 }
1868
1869 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1870
1871 return -EINVAL;
1872 }
1873
1874 static int
vc4_hdmi_encoder_compute_config(const struct vc4_hdmi * vc4_hdmi,struct vc4_hdmi_connector_state * vc4_state,const struct drm_display_mode * mode)1875 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1876 struct vc4_hdmi_connector_state *vc4_state,
1877 const struct drm_display_mode *mode)
1878 {
1879 struct drm_device *dev = vc4_hdmi->connector.dev;
1880 struct drm_connector_state *conn_state = &vc4_state->base;
1881 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1882 unsigned int bpc;
1883 int ret;
1884
1885 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1886 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1887
1888 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1889 mode, bpc);
1890 if (ret)
1891 continue;
1892
1893 vc4_state->output_bpc = bpc;
1894
1895 drm_dbg(dev,
1896 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1897 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1898 vc4_state->output_bpc,
1899 vc4_hdmi_output_fmt_str(vc4_state->output_format),
1900 vc4_state->tmds_char_rate);
1901
1902 break;
1903 }
1904
1905 return ret;
1906 }
1907
1908 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1909 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1910
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1911 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1912 struct drm_crtc_state *crtc_state,
1913 struct drm_connector_state *conn_state)
1914 {
1915 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1916 struct drm_connector *connector = &vc4_hdmi->connector;
1917 struct drm_connector_state *old_conn_state =
1918 drm_atomic_get_old_connector_state(conn_state->state, connector);
1919 struct vc4_hdmi_connector_state *old_vc4_state =
1920 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1921 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1922 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1923 unsigned long long tmds_char_rate = mode->clock * 1000;
1924 unsigned long long tmds_bit_rate;
1925 int ret;
1926
1927 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1928 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1929 /* Only try to fixup DBLCLK modes to get 480i and 576i
1930 * working.
1931 * A generic solution for all modes with odd horizontal
1932 * timing values seems impossible based on trying to
1933 * solve it for 1366x768 monitors.
1934 */
1935 if ((mode->hsync_start - mode->hdisplay) & 1)
1936 mode->hsync_start--;
1937 if ((mode->hsync_end - mode->hsync_start) & 1)
1938 mode->hsync_end--;
1939 }
1940
1941 /* Now check whether we still have odd values remaining */
1942 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1943 (mode->hsync_end % 2) || (mode->htotal % 2))
1944 return -EINVAL;
1945 }
1946
1947 /*
1948 * The 1440p@60 pixel rate is in the same range than the first
1949 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1950 * bandwidth). Slightly lower the frequency to bring it out of
1951 * the WiFi range.
1952 */
1953 tmds_bit_rate = tmds_char_rate * 10;
1954 if (vc4_hdmi->disable_wifi_frequencies &&
1955 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1956 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1957 mode->clock = 238560;
1958 tmds_char_rate = mode->clock * 1000;
1959 }
1960
1961 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1962 if (ret)
1963 return ret;
1964
1965 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1966 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1967 vc4_state->output_format != old_vc4_state->output_format)
1968 crtc_state->mode_changed = true;
1969
1970 return 0;
1971 }
1972
1973 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)1974 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1975 const struct drm_display_mode *mode)
1976 {
1977 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1978
1979 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1980 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1981 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1982 (mode->hsync_end % 2) || (mode->htotal % 2)))
1983 return MODE_H_ILLEGAL;
1984
1985 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
1986 }
1987
1988 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1989 .atomic_check = vc4_hdmi_encoder_atomic_check,
1990 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1991 .mode_valid = vc4_hdmi_encoder_mode_valid,
1992 };
1993
vc4_hdmi_late_register(struct drm_encoder * encoder)1994 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1995 {
1996 struct drm_device *drm = encoder->dev;
1997 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1998 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1999 int ret;
2000
2001 ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name,
2002 vc4_hdmi_debugfs_regs,
2003 vc4_hdmi);
2004 if (ret)
2005 return ret;
2006
2007 return 0;
2008 }
2009
2010 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2011 .late_register = vc4_hdmi_late_register,
2012 };
2013
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)2014 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2015 {
2016 int i;
2017 u32 channel_map = 0;
2018
2019 for (i = 0; i < 8; i++) {
2020 if (channel_mask & BIT(i))
2021 channel_map |= i << (3 * i);
2022 }
2023 return channel_map;
2024 }
2025
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)2026 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2027 {
2028 int i;
2029 u32 channel_map = 0;
2030
2031 for (i = 0; i < 8; i++) {
2032 if (channel_mask & BIT(i))
2033 channel_map |= i << (4 * i);
2034 }
2035 return channel_map;
2036 }
2037
vc5_hdmi_hp_detect(struct vc4_hdmi * vc4_hdmi)2038 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2039 {
2040 struct drm_device *drm = vc4_hdmi->connector.dev;
2041 unsigned long flags;
2042 u32 hotplug;
2043 int idx;
2044
2045 if (!drm_dev_enter(drm, &idx))
2046 return false;
2047
2048 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2049 hotplug = HDMI_READ(HDMI_HOTPLUG);
2050 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2051
2052 drm_dev_exit(idx);
2053
2054 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2055 }
2056
2057 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)2058 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2059 unsigned int samplerate)
2060 {
2061 struct drm_device *drm = vc4_hdmi->connector.dev;
2062 u32 hsm_clock;
2063 unsigned long flags;
2064 unsigned long n, m;
2065 int idx;
2066
2067 if (!drm_dev_enter(drm, &idx))
2068 return;
2069
2070 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2071 rational_best_approximation(hsm_clock, samplerate,
2072 VC4_HD_MAI_SMP_N_MASK >>
2073 VC4_HD_MAI_SMP_N_SHIFT,
2074 (VC4_HD_MAI_SMP_M_MASK >>
2075 VC4_HD_MAI_SMP_M_SHIFT) + 1,
2076 &n, &m);
2077
2078 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2079 HDMI_WRITE(HDMI_MAI_SMP,
2080 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2081 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2082 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2083
2084 drm_dev_exit(idx);
2085 }
2086
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)2087 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2088 {
2089 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2090 u32 n, cts;
2091 u64 tmp;
2092
2093 lockdep_assert_held(&vc4_hdmi->mutex);
2094 lockdep_assert_held(&vc4_hdmi->hw_lock);
2095
2096 n = 128 * samplerate / 1000;
2097 tmp = (u64)(mode->clock * 1000) * n;
2098 do_div(tmp, 128 * samplerate);
2099 cts = tmp;
2100
2101 HDMI_WRITE(HDMI_CRP_CFG,
2102 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2103 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2104
2105 /*
2106 * We could get slightly more accurate clocks in some cases by
2107 * providing a CTS_1 value. The two CTS values are alternated
2108 * between based on the period fields
2109 */
2110 HDMI_WRITE(HDMI_CTS_0, cts);
2111 HDMI_WRITE(HDMI_CTS_1, cts);
2112 }
2113
dai_to_hdmi(struct snd_soc_dai * dai)2114 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2115 {
2116 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2117
2118 return snd_soc_card_get_drvdata(card);
2119 }
2120
vc4_hdmi_audio_can_stream(struct vc4_hdmi * vc4_hdmi)2121 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2122 {
2123 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2124
2125 lockdep_assert_held(&vc4_hdmi->mutex);
2126
2127 /*
2128 * If the encoder is currently in DVI mode, treat the codec DAI
2129 * as missing.
2130 */
2131 if (!display->is_hdmi)
2132 return false;
2133
2134 return true;
2135 }
2136
vc4_hdmi_audio_startup(struct device * dev,void * data)2137 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2138 {
2139 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2140 struct drm_device *drm = vc4_hdmi->connector.dev;
2141 unsigned long flags;
2142 int ret = 0;
2143 int idx;
2144
2145 mutex_lock(&vc4_hdmi->mutex);
2146
2147 if (!drm_dev_enter(drm, &idx)) {
2148 ret = -ENODEV;
2149 goto out;
2150 }
2151
2152 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2153 ret = -ENODEV;
2154 goto out_dev_exit;
2155 }
2156
2157 vc4_hdmi->audio.streaming = true;
2158
2159 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2160 HDMI_WRITE(HDMI_MAI_CTL,
2161 VC4_HD_MAI_CTL_RESET |
2162 VC4_HD_MAI_CTL_FLUSH |
2163 VC4_HD_MAI_CTL_DLATE |
2164 VC4_HD_MAI_CTL_ERRORE |
2165 VC4_HD_MAI_CTL_ERRORF);
2166 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2167
2168 if (vc4_hdmi->variant->phy_rng_enable)
2169 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2170
2171 out_dev_exit:
2172 drm_dev_exit(idx);
2173 out:
2174 mutex_unlock(&vc4_hdmi->mutex);
2175
2176 return ret;
2177 }
2178
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)2179 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2180 {
2181 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2182 struct device *dev = &vc4_hdmi->pdev->dev;
2183 unsigned long flags;
2184 int ret;
2185
2186 lockdep_assert_held(&vc4_hdmi->mutex);
2187
2188 vc4_hdmi->audio.streaming = false;
2189 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2190 if (ret)
2191 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2192
2193 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2194
2195 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2196 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2197 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2198
2199 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2200 }
2201
vc4_hdmi_audio_shutdown(struct device * dev,void * data)2202 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2203 {
2204 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2205 struct drm_device *drm = vc4_hdmi->connector.dev;
2206 unsigned long flags;
2207 int idx;
2208
2209 mutex_lock(&vc4_hdmi->mutex);
2210
2211 if (!drm_dev_enter(drm, &idx))
2212 goto out;
2213
2214 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2215
2216 HDMI_WRITE(HDMI_MAI_CTL,
2217 VC4_HD_MAI_CTL_DLATE |
2218 VC4_HD_MAI_CTL_ERRORE |
2219 VC4_HD_MAI_CTL_ERRORF);
2220
2221 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2222
2223 if (vc4_hdmi->variant->phy_rng_disable)
2224 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2225
2226 vc4_hdmi->audio.streaming = false;
2227 vc4_hdmi_audio_reset(vc4_hdmi);
2228
2229 drm_dev_exit(idx);
2230
2231 out:
2232 mutex_unlock(&vc4_hdmi->mutex);
2233 }
2234
sample_rate_to_mai_fmt(int samplerate)2235 static int sample_rate_to_mai_fmt(int samplerate)
2236 {
2237 switch (samplerate) {
2238 case 8000:
2239 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2240 case 11025:
2241 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2242 case 12000:
2243 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2244 case 16000:
2245 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2246 case 22050:
2247 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2248 case 24000:
2249 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2250 case 32000:
2251 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2252 case 44100:
2253 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2254 case 48000:
2255 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2256 case 64000:
2257 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2258 case 88200:
2259 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2260 case 96000:
2261 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2262 case 128000:
2263 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2264 case 176400:
2265 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2266 case 192000:
2267 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2268 default:
2269 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2270 }
2271 }
2272
2273 /* HDMI audio codec callbacks */
vc4_hdmi_audio_prepare(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2274 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2275 struct hdmi_codec_daifmt *daifmt,
2276 struct hdmi_codec_params *params)
2277 {
2278 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2279 struct drm_device *drm = vc4_hdmi->connector.dev;
2280 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2281 unsigned int sample_rate = params->sample_rate;
2282 unsigned int channels = params->channels;
2283 unsigned long flags;
2284 u32 audio_packet_config, channel_mask;
2285 u32 channel_map;
2286 u32 mai_audio_format;
2287 u32 mai_sample_rate;
2288 int ret = 0;
2289 int idx;
2290
2291 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2292 sample_rate, params->sample_width, channels);
2293
2294 mutex_lock(&vc4_hdmi->mutex);
2295
2296 if (!drm_dev_enter(drm, &idx)) {
2297 ret = -ENODEV;
2298 goto out;
2299 }
2300
2301 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2302 ret = -EINVAL;
2303 goto out_dev_exit;
2304 }
2305
2306 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2307
2308 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2309 HDMI_WRITE(HDMI_MAI_CTL,
2310 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2311 VC4_HD_MAI_CTL_WHOLSMP |
2312 VC4_HD_MAI_CTL_CHALIGN |
2313 VC4_HD_MAI_CTL_ENABLE);
2314
2315 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2316 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2317 params->channels == 8)
2318 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2319 else
2320 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2321 HDMI_WRITE(HDMI_MAI_FMT,
2322 VC4_SET_FIELD(mai_sample_rate,
2323 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2324 VC4_SET_FIELD(mai_audio_format,
2325 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2326
2327 /* The B frame identifier should match the value used by alsa-lib (8) */
2328 audio_packet_config =
2329 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2330 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2331 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2332
2333 channel_mask = GENMASK(channels - 1, 0);
2334 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2335 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2336
2337 /* Set the MAI threshold */
2338 HDMI_WRITE(HDMI_MAI_THR,
2339 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2340 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2341 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2342 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2343
2344 HDMI_WRITE(HDMI_MAI_CONFIG,
2345 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2346 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2347 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2348
2349 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2350 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2351 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2352
2353 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2354
2355 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2356
2357 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
2358 vc4_hdmi_set_audio_infoframe(encoder);
2359
2360 out_dev_exit:
2361 drm_dev_exit(idx);
2362 out:
2363 mutex_unlock(&vc4_hdmi->mutex);
2364
2365 return ret;
2366 }
2367
2368 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2369 .name = "vc4-hdmi-cpu-dai-component",
2370 .legacy_dai_naming = 1,
2371 };
2372
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)2373 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2374 {
2375 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2376
2377 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2378
2379 return 0;
2380 }
2381
2382 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2383 .name = "vc4-hdmi-cpu-dai",
2384 .probe = vc4_hdmi_audio_cpu_dai_probe,
2385 .playback = {
2386 .stream_name = "Playback",
2387 .channels_min = 1,
2388 .channels_max = 8,
2389 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2390 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2391 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2392 SNDRV_PCM_RATE_192000,
2393 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2394 },
2395 };
2396
2397 static const struct snd_dmaengine_pcm_config pcm_conf = {
2398 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2399 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2400 };
2401
vc4_hdmi_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)2402 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2403 uint8_t *buf, size_t len)
2404 {
2405 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2406 struct drm_connector *connector = &vc4_hdmi->connector;
2407
2408 mutex_lock(&vc4_hdmi->mutex);
2409 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2410 mutex_unlock(&vc4_hdmi->mutex);
2411
2412 return 0;
2413 }
2414
2415 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2416 .get_eld = vc4_hdmi_audio_get_eld,
2417 .prepare = vc4_hdmi_audio_prepare,
2418 .audio_shutdown = vc4_hdmi_audio_shutdown,
2419 .audio_startup = vc4_hdmi_audio_startup,
2420 };
2421
2422 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2423 .ops = &vc4_hdmi_codec_ops,
2424 .max_i2s_channels = 8,
2425 .i2s = 1,
2426 };
2427
vc4_hdmi_audio_codec_release(void * ptr)2428 static void vc4_hdmi_audio_codec_release(void *ptr)
2429 {
2430 struct vc4_hdmi *vc4_hdmi = ptr;
2431
2432 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2433 vc4_hdmi->audio.codec_pdev = NULL;
2434 }
2435
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)2436 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2437 {
2438 const struct vc4_hdmi_register *mai_data =
2439 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2440 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2441 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2442 struct device *dev = &vc4_hdmi->pdev->dev;
2443 struct platform_device *codec_pdev;
2444 const __be32 *addr;
2445 int index, len;
2446 int ret;
2447
2448 /*
2449 * ASoC makes it a bit hard to retrieve a pointer to the
2450 * vc4_hdmi structure. Registering the card will overwrite our
2451 * device drvdata with a pointer to the snd_soc_card structure,
2452 * which can then be used to retrieve whatever drvdata we want
2453 * to associate.
2454 *
2455 * However, that doesn't fly in the case where we wouldn't
2456 * register an ASoC card (because of an old DT that is missing
2457 * the dmas properties for example), then the card isn't
2458 * registered and the device drvdata wouldn't be set.
2459 *
2460 * We can deal with both cases by making sure a snd_soc_card
2461 * pointer and a vc4_hdmi structure are pointing to the same
2462 * memory address, so we can treat them indistinctly without any
2463 * issue.
2464 */
2465 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2466 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2467
2468 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2469 dev_warn(dev,
2470 "'dmas' DT property is missing or empty, no HDMI audio\n");
2471 return 0;
2472 }
2473
2474 if (mai_data->reg != VC4_HD) {
2475 WARN_ONCE(true, "MAI isn't in the HD block\n");
2476 return -EINVAL;
2477 }
2478
2479 /*
2480 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2481 * the bus address specified in the DT, because the physical address
2482 * (the one returned by platform_get_resource()) is not appropriate
2483 * for DMA transfers.
2484 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2485 */
2486 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2487 /* Before BCM2711, we don't have a named register range */
2488 if (index < 0)
2489 index = 1;
2490
2491 addr = of_get_address(dev->of_node, index, NULL, NULL);
2492
2493 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2494 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2495 vc4_hdmi->audio.dma_data.maxburst = 2;
2496
2497 /*
2498 * NOTE: Strictly speaking, we should probably use a DRM-managed
2499 * registration there to avoid removing all the audio components
2500 * by the time the driver doesn't have any user anymore.
2501 *
2502 * However, the ASoC core uses a number of devm_kzalloc calls
2503 * when registering, even when using non-device-managed
2504 * functions (such as in snd_soc_register_component()).
2505 *
2506 * If we call snd_soc_unregister_component() in a DRM-managed
2507 * action, the device-managed actions have already been executed
2508 * and thus we would access memory that has been freed.
2509 *
2510 * Using device-managed hooks here probably leaves us open to a
2511 * bunch of issues if userspace still has a handle on the ALSA
2512 * device when the device is removed. However, this is mitigated
2513 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2514 * path to prevent the access to the device resources if it
2515 * isn't there anymore.
2516 *
2517 * Then, the vc4_hdmi structure is DRM-managed and thus only
2518 * freed whenever the last user has closed the DRM device file.
2519 * It should thus outlive ALSA in most situations.
2520 */
2521 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2522 if (ret) {
2523 dev_err(dev, "Could not register PCM component: %d\n", ret);
2524 return ret;
2525 }
2526
2527 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2528 &vc4_hdmi_audio_cpu_dai_drv, 1);
2529 if (ret) {
2530 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2531 return ret;
2532 }
2533
2534 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2535 PLATFORM_DEVID_AUTO,
2536 &vc4_hdmi_codec_pdata,
2537 sizeof(vc4_hdmi_codec_pdata));
2538 if (IS_ERR(codec_pdev)) {
2539 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2540 return PTR_ERR(codec_pdev);
2541 }
2542 vc4_hdmi->audio.codec_pdev = codec_pdev;
2543
2544 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2545 if (ret)
2546 return ret;
2547
2548 dai_link->cpus = &vc4_hdmi->audio.cpu;
2549 dai_link->codecs = &vc4_hdmi->audio.codec;
2550 dai_link->platforms = &vc4_hdmi->audio.platform;
2551
2552 dai_link->num_cpus = 1;
2553 dai_link->num_codecs = 1;
2554 dai_link->num_platforms = 1;
2555
2556 dai_link->name = "MAI";
2557 dai_link->stream_name = "MAI PCM";
2558 dai_link->codecs->dai_name = "i2s-hifi";
2559 dai_link->cpus->dai_name = dev_name(dev);
2560 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2561 dai_link->platforms->name = dev_name(dev);
2562
2563 card->dai_link = dai_link;
2564 card->num_links = 1;
2565 card->name = vc4_hdmi->variant->card_name;
2566 card->driver_name = "vc4-hdmi";
2567 card->dev = dev;
2568 card->owner = THIS_MODULE;
2569
2570 /*
2571 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2572 * stores a pointer to the snd card object in dev->driver_data. This
2573 * means we cannot use it for something else. The hdmi back-pointer is
2574 * now stored in card->drvdata and should be retrieved with
2575 * snd_soc_card_get_drvdata() if needed.
2576 */
2577 snd_soc_card_set_drvdata(card, vc4_hdmi);
2578 ret = devm_snd_soc_register_card(dev, card);
2579 if (ret)
2580 dev_err_probe(dev, ret, "Could not register sound card\n");
2581
2582 return ret;
2583
2584 }
2585
vc4_hdmi_hpd_irq_thread(int irq,void * priv)2586 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2587 {
2588 struct vc4_hdmi *vc4_hdmi = priv;
2589 struct drm_connector *connector = &vc4_hdmi->connector;
2590 struct drm_device *dev = connector->dev;
2591
2592 if (dev && dev->registered)
2593 drm_connector_helper_hpd_irq_event(connector);
2594
2595 return IRQ_HANDLED;
2596 }
2597
vc4_hdmi_hotplug_init(struct vc4_hdmi * vc4_hdmi)2598 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2599 {
2600 struct drm_connector *connector = &vc4_hdmi->connector;
2601 struct platform_device *pdev = vc4_hdmi->pdev;
2602 int ret;
2603
2604 if (vc4_hdmi->variant->external_irq_controller) {
2605 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2606 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2607
2608 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2609 NULL,
2610 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2611 "vc4 hdmi hpd connected", vc4_hdmi);
2612 if (ret)
2613 return ret;
2614
2615 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2616 NULL,
2617 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2618 "vc4 hdmi hpd disconnected", vc4_hdmi);
2619 if (ret)
2620 return ret;
2621
2622 connector->polled = DRM_CONNECTOR_POLL_HPD;
2623 }
2624
2625 return 0;
2626 }
2627
2628 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_rx_thread(int irq,void * priv)2629 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2630 {
2631 struct vc4_hdmi *vc4_hdmi = priv;
2632
2633 if (vc4_hdmi->cec_rx_msg.len)
2634 cec_received_msg(vc4_hdmi->cec_adap,
2635 &vc4_hdmi->cec_rx_msg);
2636
2637 return IRQ_HANDLED;
2638 }
2639
vc4_cec_irq_handler_tx_thread(int irq,void * priv)2640 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2641 {
2642 struct vc4_hdmi *vc4_hdmi = priv;
2643
2644 if (vc4_hdmi->cec_tx_ok) {
2645 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2646 0, 0, 0, 0);
2647 } else {
2648 /*
2649 * This CEC implementation makes 1 retry, so if we
2650 * get a NACK, then that means it made 2 attempts.
2651 */
2652 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2653 0, 2, 0, 0);
2654 }
2655 return IRQ_HANDLED;
2656 }
2657
vc4_cec_irq_handler_thread(int irq,void * priv)2658 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2659 {
2660 struct vc4_hdmi *vc4_hdmi = priv;
2661 irqreturn_t ret;
2662
2663 if (vc4_hdmi->cec_irq_was_rx)
2664 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2665 else
2666 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2667
2668 return ret;
2669 }
2670
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)2671 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2672 {
2673 struct drm_device *dev = vc4_hdmi->connector.dev;
2674 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2675 unsigned int i;
2676
2677 lockdep_assert_held(&vc4_hdmi->hw_lock);
2678
2679 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2680 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2681
2682 if (msg->len > 16) {
2683 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2684 return;
2685 }
2686
2687 for (i = 0; i < msg->len; i += 4) {
2688 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2689
2690 msg->msg[i] = val & 0xff;
2691 msg->msg[i + 1] = (val >> 8) & 0xff;
2692 msg->msg[i + 2] = (val >> 16) & 0xff;
2693 msg->msg[i + 3] = (val >> 24) & 0xff;
2694 }
2695 }
2696
vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi * vc4_hdmi)2697 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2698 {
2699 u32 cntrl1;
2700
2701 /*
2702 * We don't need to protect the register access using
2703 * drm_dev_enter() there because the interrupt handler lifetime
2704 * is tied to the device itself, and not to the DRM device.
2705 *
2706 * So when the device will be gone, one of the first thing we
2707 * will be doing will be to unregister the interrupt handler,
2708 * and then unregister the DRM device. drm_dev_enter() would
2709 * thus always succeed if we are here.
2710 */
2711
2712 lockdep_assert_held(&vc4_hdmi->hw_lock);
2713
2714 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2715 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2716 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2717 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2718
2719 return IRQ_WAKE_THREAD;
2720 }
2721
vc4_cec_irq_handler_tx_bare(int irq,void * priv)2722 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2723 {
2724 struct vc4_hdmi *vc4_hdmi = priv;
2725 irqreturn_t ret;
2726
2727 spin_lock(&vc4_hdmi->hw_lock);
2728 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2729 spin_unlock(&vc4_hdmi->hw_lock);
2730
2731 return ret;
2732 }
2733
vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi * vc4_hdmi)2734 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2735 {
2736 u32 cntrl1;
2737
2738 lockdep_assert_held(&vc4_hdmi->hw_lock);
2739
2740 /*
2741 * We don't need to protect the register access using
2742 * drm_dev_enter() there because the interrupt handler lifetime
2743 * is tied to the device itself, and not to the DRM device.
2744 *
2745 * So when the device will be gone, one of the first thing we
2746 * will be doing will be to unregister the interrupt handler,
2747 * and then unregister the DRM device. drm_dev_enter() would
2748 * thus always succeed if we are here.
2749 */
2750
2751 vc4_hdmi->cec_rx_msg.len = 0;
2752 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2753 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2754 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2755 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2756 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2757
2758 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2759
2760 return IRQ_WAKE_THREAD;
2761 }
2762
vc4_cec_irq_handler_rx_bare(int irq,void * priv)2763 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2764 {
2765 struct vc4_hdmi *vc4_hdmi = priv;
2766 irqreturn_t ret;
2767
2768 spin_lock(&vc4_hdmi->hw_lock);
2769 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2770 spin_unlock(&vc4_hdmi->hw_lock);
2771
2772 return ret;
2773 }
2774
vc4_cec_irq_handler(int irq,void * priv)2775 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2776 {
2777 struct vc4_hdmi *vc4_hdmi = priv;
2778 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2779 irqreturn_t ret;
2780 u32 cntrl5;
2781
2782 /*
2783 * We don't need to protect the register access using
2784 * drm_dev_enter() there because the interrupt handler lifetime
2785 * is tied to the device itself, and not to the DRM device.
2786 *
2787 * So when the device will be gone, one of the first thing we
2788 * will be doing will be to unregister the interrupt handler,
2789 * and then unregister the DRM device. drm_dev_enter() would
2790 * thus always succeed if we are here.
2791 */
2792
2793 if (!(stat & VC4_HDMI_CPU_CEC))
2794 return IRQ_NONE;
2795
2796 spin_lock(&vc4_hdmi->hw_lock);
2797 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2798 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2799 if (vc4_hdmi->cec_irq_was_rx)
2800 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2801 else
2802 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2803
2804 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2805 spin_unlock(&vc4_hdmi->hw_lock);
2806
2807 return ret;
2808 }
2809
vc4_hdmi_cec_enable(struct cec_adapter * adap)2810 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2811 {
2812 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2813 struct drm_device *drm = vc4_hdmi->connector.dev;
2814 /* clock period in microseconds */
2815 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2816 unsigned long flags;
2817 u32 val;
2818 int ret;
2819 int idx;
2820
2821 if (!drm_dev_enter(drm, &idx))
2822 /*
2823 * We can't return an error code, because the CEC
2824 * framework will emit WARN_ON messages at unbind
2825 * otherwise.
2826 */
2827 return 0;
2828
2829 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2830 if (ret) {
2831 drm_dev_exit(idx);
2832 return ret;
2833 }
2834
2835 mutex_lock(&vc4_hdmi->mutex);
2836
2837 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2838
2839 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2840 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2841 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2842 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2843 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2844 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2845
2846 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2847 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2848 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2849 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2850 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2851 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2852 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2853 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2854 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2855 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2856 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2857 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2858 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2859 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2860 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2861 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2862 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2863 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2864 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2865
2866 if (!vc4_hdmi->variant->external_irq_controller)
2867 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2868
2869 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2870
2871 mutex_unlock(&vc4_hdmi->mutex);
2872 drm_dev_exit(idx);
2873
2874 return 0;
2875 }
2876
vc4_hdmi_cec_disable(struct cec_adapter * adap)2877 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2878 {
2879 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2880 struct drm_device *drm = vc4_hdmi->connector.dev;
2881 unsigned long flags;
2882 int idx;
2883
2884 if (!drm_dev_enter(drm, &idx))
2885 /*
2886 * We can't return an error code, because the CEC
2887 * framework will emit WARN_ON messages at unbind
2888 * otherwise.
2889 */
2890 return 0;
2891
2892 mutex_lock(&vc4_hdmi->mutex);
2893
2894 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2895
2896 if (!vc4_hdmi->variant->external_irq_controller)
2897 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2898
2899 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2900 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2901
2902 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2903
2904 mutex_unlock(&vc4_hdmi->mutex);
2905
2906 pm_runtime_put(&vc4_hdmi->pdev->dev);
2907
2908 drm_dev_exit(idx);
2909
2910 return 0;
2911 }
2912
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)2913 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2914 {
2915 if (enable)
2916 return vc4_hdmi_cec_enable(adap);
2917 else
2918 return vc4_hdmi_cec_disable(adap);
2919 }
2920
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)2921 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2922 {
2923 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2924 struct drm_device *drm = vc4_hdmi->connector.dev;
2925 unsigned long flags;
2926 int idx;
2927
2928 if (!drm_dev_enter(drm, &idx))
2929 /*
2930 * We can't return an error code, because the CEC
2931 * framework will emit WARN_ON messages at unbind
2932 * otherwise.
2933 */
2934 return 0;
2935
2936 mutex_lock(&vc4_hdmi->mutex);
2937 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2938 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2939 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2940 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2941 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2942 mutex_unlock(&vc4_hdmi->mutex);
2943
2944 drm_dev_exit(idx);
2945
2946 return 0;
2947 }
2948
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)2949 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2950 u32 signal_free_time, struct cec_msg *msg)
2951 {
2952 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2953 struct drm_device *dev = vc4_hdmi->connector.dev;
2954 unsigned long flags;
2955 u32 val;
2956 unsigned int i;
2957 int idx;
2958
2959 if (!drm_dev_enter(dev, &idx))
2960 return -ENODEV;
2961
2962 if (msg->len > 16) {
2963 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2964 drm_dev_exit(idx);
2965 return -ENOMEM;
2966 }
2967
2968 mutex_lock(&vc4_hdmi->mutex);
2969
2970 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2971
2972 for (i = 0; i < msg->len; i += 4)
2973 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2974 (msg->msg[i]) |
2975 (msg->msg[i + 1] << 8) |
2976 (msg->msg[i + 2] << 16) |
2977 (msg->msg[i + 3] << 24));
2978
2979 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2980 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2981 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2982 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2983 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2984 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2985
2986 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2987
2988 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2989 mutex_unlock(&vc4_hdmi->mutex);
2990 drm_dev_exit(idx);
2991
2992 return 0;
2993 }
2994
2995 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2996 .adap_enable = vc4_hdmi_cec_adap_enable,
2997 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2998 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2999 };
3000
vc4_hdmi_cec_release(void * ptr)3001 static void vc4_hdmi_cec_release(void *ptr)
3002 {
3003 struct vc4_hdmi *vc4_hdmi = ptr;
3004
3005 cec_unregister_adapter(vc4_hdmi->cec_adap);
3006 vc4_hdmi->cec_adap = NULL;
3007 }
3008
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)3009 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3010 {
3011 struct cec_connector_info conn_info;
3012 struct platform_device *pdev = vc4_hdmi->pdev;
3013 struct device *dev = &pdev->dev;
3014 int ret;
3015
3016 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
3017 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3018 return 0;
3019 }
3020
3021 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3022 vc4_hdmi,
3023 vc4_hdmi->variant->card_name,
3024 CEC_CAP_DEFAULTS |
3025 CEC_CAP_CONNECTOR_INFO, 1);
3026 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3027 if (ret < 0)
3028 return ret;
3029
3030 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3031 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3032
3033 if (vc4_hdmi->variant->external_irq_controller) {
3034 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3035 vc4_cec_irq_handler_rx_bare,
3036 vc4_cec_irq_handler_rx_thread, 0,
3037 "vc4 hdmi cec rx", vc4_hdmi);
3038 if (ret)
3039 goto err_delete_cec_adap;
3040
3041 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3042 vc4_cec_irq_handler_tx_bare,
3043 vc4_cec_irq_handler_tx_thread, 0,
3044 "vc4 hdmi cec tx", vc4_hdmi);
3045 if (ret)
3046 goto err_delete_cec_adap;
3047 } else {
3048 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3049 vc4_cec_irq_handler,
3050 vc4_cec_irq_handler_thread, 0,
3051 "vc4 hdmi cec", vc4_hdmi);
3052 if (ret)
3053 goto err_delete_cec_adap;
3054 }
3055
3056 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3057 if (ret < 0)
3058 goto err_delete_cec_adap;
3059
3060 /*
3061 * NOTE: Strictly speaking, we should probably use a DRM-managed
3062 * registration there to avoid removing the CEC adapter by the
3063 * time the DRM driver doesn't have any user anymore.
3064 *
3065 * However, the CEC framework already cleans up the CEC adapter
3066 * only when the last user has closed its file descriptor, so we
3067 * don't need to handle it in DRM.
3068 *
3069 * By the time the device-managed hook is executed, we will give
3070 * up our reference to the CEC adapter and therefore don't
3071 * really care when it's actually freed.
3072 *
3073 * There's still a problematic sequence: if we unregister our
3074 * CEC adapter, but the userspace keeps a handle on the CEC
3075 * adapter but not the DRM device for some reason. In such a
3076 * case, our vc4_hdmi structure will be freed, but the
3077 * cec_adapter structure will have a dangling pointer to what
3078 * used to be our HDMI controller. If we get a CEC call at that
3079 * moment, we could end up with a use-after-free. Fortunately,
3080 * the CEC framework already handles this too, by calling
3081 * cec_is_registered() in cec_ioctl() and cec_poll().
3082 */
3083 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3084 if (ret)
3085 return ret;
3086
3087 return 0;
3088
3089 err_delete_cec_adap:
3090 cec_delete_adapter(vc4_hdmi->cec_adap);
3091
3092 return ret;
3093 }
3094 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)3095 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3096 {
3097 return 0;
3098 }
3099 #endif
3100
vc4_hdmi_free_regset(struct drm_device * drm,void * ptr)3101 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3102 {
3103 struct debugfs_reg32 *regs = ptr;
3104
3105 kfree(regs);
3106 }
3107
vc4_hdmi_build_regset(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)3108 static int vc4_hdmi_build_regset(struct drm_device *drm,
3109 struct vc4_hdmi *vc4_hdmi,
3110 struct debugfs_regset32 *regset,
3111 enum vc4_hdmi_regs reg)
3112 {
3113 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3114 struct debugfs_reg32 *regs, *new_regs;
3115 unsigned int count = 0;
3116 unsigned int i;
3117 int ret;
3118
3119 regs = kcalloc(variant->num_registers, sizeof(*regs),
3120 GFP_KERNEL);
3121 if (!regs)
3122 return -ENOMEM;
3123
3124 for (i = 0; i < variant->num_registers; i++) {
3125 const struct vc4_hdmi_register *field = &variant->registers[i];
3126
3127 if (field->reg != reg)
3128 continue;
3129
3130 regs[count].name = field->name;
3131 regs[count].offset = field->offset;
3132 count++;
3133 }
3134
3135 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3136 if (!new_regs)
3137 return -ENOMEM;
3138
3139 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3140 regset->regs = new_regs;
3141 regset->nregs = count;
3142
3143 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3144 if (ret)
3145 return ret;
3146
3147 return 0;
3148 }
3149
vc4_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)3150 static int vc4_hdmi_init_resources(struct drm_device *drm,
3151 struct vc4_hdmi *vc4_hdmi)
3152 {
3153 struct platform_device *pdev = vc4_hdmi->pdev;
3154 struct device *dev = &pdev->dev;
3155 int ret;
3156
3157 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3158 if (IS_ERR(vc4_hdmi->hdmicore_regs))
3159 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3160
3161 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3162 if (IS_ERR(vc4_hdmi->hd_regs))
3163 return PTR_ERR(vc4_hdmi->hd_regs);
3164
3165 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3166 if (ret)
3167 return ret;
3168
3169 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3170 if (ret)
3171 return ret;
3172
3173 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3174 if (IS_ERR(vc4_hdmi->pixel_clock)) {
3175 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3176 if (ret != -EPROBE_DEFER)
3177 DRM_ERROR("Failed to get pixel clock\n");
3178 return ret;
3179 }
3180
3181 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3182 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3183 DRM_ERROR("Failed to get HDMI state machine clock\n");
3184 return PTR_ERR(vc4_hdmi->hsm_clock);
3185 }
3186
3187 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3188 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3189
3190 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
3191 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
3192 DRM_ERROR("Failed to get HDMI state machine clock\n");
3193 return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
3194 }
3195
3196 return 0;
3197 }
3198
vc5_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)3199 static int vc5_hdmi_init_resources(struct drm_device *drm,
3200 struct vc4_hdmi *vc4_hdmi)
3201 {
3202 struct platform_device *pdev = vc4_hdmi->pdev;
3203 struct device *dev = &pdev->dev;
3204 struct resource *res;
3205 int ret;
3206
3207 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3208 if (!res)
3209 return -ENODEV;
3210
3211 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3212 resource_size(res));
3213 if (!vc4_hdmi->hdmicore_regs)
3214 return -ENOMEM;
3215
3216 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3217 if (!res)
3218 return -ENODEV;
3219
3220 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3221 if (!vc4_hdmi->hd_regs)
3222 return -ENOMEM;
3223
3224 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3225 if (!res)
3226 return -ENODEV;
3227
3228 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3229 if (!vc4_hdmi->cec_regs)
3230 return -ENOMEM;
3231
3232 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3233 if (!res)
3234 return -ENODEV;
3235
3236 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3237 if (!vc4_hdmi->csc_regs)
3238 return -ENOMEM;
3239
3240 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3241 if (!res)
3242 return -ENODEV;
3243
3244 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3245 if (!vc4_hdmi->dvp_regs)
3246 return -ENOMEM;
3247
3248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3249 if (!res)
3250 return -ENODEV;
3251
3252 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3253 if (!vc4_hdmi->phy_regs)
3254 return -ENOMEM;
3255
3256 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3257 if (!res)
3258 return -ENODEV;
3259
3260 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3261 if (!vc4_hdmi->ram_regs)
3262 return -ENOMEM;
3263
3264 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3265 if (!res)
3266 return -ENODEV;
3267
3268 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3269 if (!vc4_hdmi->rm_regs)
3270 return -ENOMEM;
3271
3272 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3273 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3274 DRM_ERROR("Failed to get HDMI state machine clock\n");
3275 return PTR_ERR(vc4_hdmi->hsm_clock);
3276 }
3277
3278 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
3279 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
3280 DRM_ERROR("Failed to get HDMI state machine clock\n");
3281 return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
3282 }
3283
3284 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3285 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3286 DRM_ERROR("Failed to get pixel bvb clock\n");
3287 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3288 }
3289
3290 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3291 if (IS_ERR(vc4_hdmi->audio_clock)) {
3292 DRM_ERROR("Failed to get audio clock\n");
3293 return PTR_ERR(vc4_hdmi->audio_clock);
3294 }
3295
3296 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3297 if (IS_ERR(vc4_hdmi->cec_clock)) {
3298 DRM_ERROR("Failed to get CEC clock\n");
3299 return PTR_ERR(vc4_hdmi->cec_clock);
3300 }
3301
3302 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3303 if (IS_ERR(vc4_hdmi->reset)) {
3304 DRM_ERROR("Failed to get HDMI reset line\n");
3305 return PTR_ERR(vc4_hdmi->reset);
3306 }
3307
3308 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3309 if (ret)
3310 return ret;
3311
3312 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3313 if (ret)
3314 return ret;
3315
3316 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3317 if (ret)
3318 return ret;
3319
3320 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3321 if (ret)
3322 return ret;
3323
3324 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3325 if (ret)
3326 return ret;
3327
3328 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3329 if (ret)
3330 return ret;
3331
3332 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3333 if (ret)
3334 return ret;
3335
3336 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3337 if (ret)
3338 return ret;
3339
3340 return 0;
3341 }
3342
vc4_hdmi_runtime_suspend(struct device * dev)3343 static int vc4_hdmi_runtime_suspend(struct device *dev)
3344 {
3345 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3346
3347 clk_disable_unprepare(vc4_hdmi->hsm_rpm_clock);
3348
3349 return 0;
3350 }
3351
vc4_hdmi_runtime_resume(struct device * dev)3352 static int vc4_hdmi_runtime_resume(struct device *dev)
3353 {
3354 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3355 unsigned long __maybe_unused flags;
3356 u32 __maybe_unused value;
3357 unsigned long rate;
3358 int ret;
3359
3360 /*
3361 * The HSM clock is in the HDMI power domain, so we need to set
3362 * its frequency while the power domain is active so that it
3363 * keeps its rate.
3364 */
3365 ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ);
3366 if (ret)
3367 return ret;
3368
3369 ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock);
3370 if (ret)
3371 return ret;
3372
3373 /*
3374 * Whenever the RaspberryPi boots without an HDMI monitor
3375 * plugged in, the firmware won't have initialized the HSM clock
3376 * rate and it will be reported as 0.
3377 *
3378 * If we try to access a register of the controller in such a
3379 * case, it will lead to a silent CPU stall. Let's make sure we
3380 * prevent such a case.
3381 */
3382 rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock);
3383 if (!rate) {
3384 ret = -EINVAL;
3385 goto err_disable_clk;
3386 }
3387
3388 if (vc4_hdmi->variant->reset)
3389 vc4_hdmi->variant->reset(vc4_hdmi);
3390
3391 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3392 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3393 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3394 /* Set the logical address to Unregistered */
3395 value |= VC4_HDMI_CEC_ADDR_MASK;
3396 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3397 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3398
3399 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3400
3401 if (!vc4_hdmi->variant->external_irq_controller) {
3402 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3403 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3404 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3405 }
3406 #endif
3407
3408 return 0;
3409
3410 err_disable_clk:
3411 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3412 return ret;
3413 }
3414
vc4_hdmi_put_ddc_device(void * ptr)3415 static void vc4_hdmi_put_ddc_device(void *ptr)
3416 {
3417 struct vc4_hdmi *vc4_hdmi = ptr;
3418
3419 put_device(&vc4_hdmi->ddc->dev);
3420 }
3421
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)3422 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3423 {
3424 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3425 struct platform_device *pdev = to_platform_device(dev);
3426 struct drm_device *drm = dev_get_drvdata(master);
3427 struct vc4_hdmi *vc4_hdmi;
3428 struct drm_encoder *encoder;
3429 struct device_node *ddc_node;
3430 int ret;
3431
3432 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3433 if (!vc4_hdmi)
3434 return -ENOMEM;
3435
3436 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3437 if (ret)
3438 return ret;
3439
3440 spin_lock_init(&vc4_hdmi->hw_lock);
3441 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3442
3443 dev_set_drvdata(dev, vc4_hdmi);
3444 encoder = &vc4_hdmi->encoder.base;
3445 vc4_hdmi->encoder.type = variant->encoder_type;
3446 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3447 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3448 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3449 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3450 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3451 vc4_hdmi->pdev = pdev;
3452 vc4_hdmi->variant = variant;
3453
3454 /*
3455 * Since we don't know the state of the controller and its
3456 * display (if any), let's assume it's always enabled.
3457 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3458 * sure it's disabled, and avoid any inconsistency.
3459 */
3460 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3461 vc4_hdmi->scdc_enabled = true;
3462
3463 ret = variant->init_resources(drm, vc4_hdmi);
3464 if (ret)
3465 return ret;
3466
3467 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3468 if (!ddc_node) {
3469 DRM_ERROR("Failed to find ddc node in device tree\n");
3470 return -ENODEV;
3471 }
3472
3473 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3474 of_node_put(ddc_node);
3475 if (!vc4_hdmi->ddc) {
3476 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3477 return -EPROBE_DEFER;
3478 }
3479
3480 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3481 if (ret)
3482 return ret;
3483
3484 /* Only use the GPIO HPD pin if present in the DT, otherwise
3485 * we'll use the HDMI core's register.
3486 */
3487 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3488 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3489 return PTR_ERR(vc4_hdmi->hpd_gpio);
3490 }
3491
3492 vc4_hdmi->disable_wifi_frequencies =
3493 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3494
3495 if (variant->max_pixel_clock == 600000000) {
3496 struct vc4_dev *vc4 = to_vc4_dev(drm);
3497 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
3498
3499 if (max_rate < 550000000)
3500 vc4_hdmi->disable_4kp60 = true;
3501 }
3502
3503 ret = devm_pm_runtime_enable(dev);
3504 if (ret)
3505 return ret;
3506
3507 /*
3508 * We need to have the device powered up at this point to call
3509 * our reset hook and for the CEC init.
3510 */
3511 ret = pm_runtime_resume_and_get(dev);
3512 if (ret)
3513 return ret;
3514
3515 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3516 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3517 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3518 clk_prepare_enable(vc4_hdmi->pixel_clock);
3519 clk_prepare_enable(vc4_hdmi->hsm_clock);
3520 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3521 }
3522
3523 ret = drmm_encoder_init(drm, encoder,
3524 &vc4_hdmi_encoder_funcs,
3525 DRM_MODE_ENCODER_TMDS,
3526 NULL);
3527 if (ret)
3528 goto err_put_runtime_pm;
3529
3530 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3531
3532 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3533 if (ret)
3534 goto err_put_runtime_pm;
3535
3536 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3537 if (ret)
3538 goto err_put_runtime_pm;
3539
3540 ret = vc4_hdmi_cec_init(vc4_hdmi);
3541 if (ret)
3542 goto err_put_runtime_pm;
3543
3544 ret = vc4_hdmi_audio_init(vc4_hdmi);
3545 if (ret)
3546 goto err_put_runtime_pm;
3547
3548 pm_runtime_put_sync(dev);
3549
3550 return 0;
3551
3552 err_put_runtime_pm:
3553 pm_runtime_put_sync(dev);
3554
3555 return ret;
3556 }
3557
3558 static const struct component_ops vc4_hdmi_ops = {
3559 .bind = vc4_hdmi_bind,
3560 };
3561
vc4_hdmi_dev_probe(struct platform_device * pdev)3562 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3563 {
3564 return component_add(&pdev->dev, &vc4_hdmi_ops);
3565 }
3566
vc4_hdmi_dev_remove(struct platform_device * pdev)3567 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3568 {
3569 component_del(&pdev->dev, &vc4_hdmi_ops);
3570 return 0;
3571 }
3572
3573 static const struct vc4_hdmi_variant bcm2835_variant = {
3574 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3575 .debugfs_name = "hdmi_regs",
3576 .card_name = "vc4-hdmi",
3577 .max_pixel_clock = 162000000,
3578 .registers = vc4_hdmi_fields,
3579 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3580
3581 .init_resources = vc4_hdmi_init_resources,
3582 .csc_setup = vc4_hdmi_csc_setup,
3583 .reset = vc4_hdmi_reset,
3584 .set_timings = vc4_hdmi_set_timings,
3585 .phy_init = vc4_hdmi_phy_init,
3586 .phy_disable = vc4_hdmi_phy_disable,
3587 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3588 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3589 .channel_map = vc4_hdmi_channel_map,
3590 .supports_hdr = false,
3591 };
3592
3593 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3594 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3595 .debugfs_name = "hdmi0_regs",
3596 .card_name = "vc4-hdmi-0",
3597 .max_pixel_clock = 600000000,
3598 .registers = vc5_hdmi_hdmi0_fields,
3599 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3600 .phy_lane_mapping = {
3601 PHY_LANE_0,
3602 PHY_LANE_1,
3603 PHY_LANE_2,
3604 PHY_LANE_CK,
3605 },
3606 .unsupported_odd_h_timings = true,
3607 .external_irq_controller = true,
3608
3609 .init_resources = vc5_hdmi_init_resources,
3610 .csc_setup = vc5_hdmi_csc_setup,
3611 .reset = vc5_hdmi_reset,
3612 .set_timings = vc5_hdmi_set_timings,
3613 .phy_init = vc5_hdmi_phy_init,
3614 .phy_disable = vc5_hdmi_phy_disable,
3615 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3616 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3617 .channel_map = vc5_hdmi_channel_map,
3618 .supports_hdr = true,
3619 .hp_detect = vc5_hdmi_hp_detect,
3620 };
3621
3622 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3623 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3624 .debugfs_name = "hdmi1_regs",
3625 .card_name = "vc4-hdmi-1",
3626 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3627 .registers = vc5_hdmi_hdmi1_fields,
3628 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3629 .phy_lane_mapping = {
3630 PHY_LANE_1,
3631 PHY_LANE_0,
3632 PHY_LANE_CK,
3633 PHY_LANE_2,
3634 },
3635 .unsupported_odd_h_timings = true,
3636 .external_irq_controller = true,
3637
3638 .init_resources = vc5_hdmi_init_resources,
3639 .csc_setup = vc5_hdmi_csc_setup,
3640 .reset = vc5_hdmi_reset,
3641 .set_timings = vc5_hdmi_set_timings,
3642 .phy_init = vc5_hdmi_phy_init,
3643 .phy_disable = vc5_hdmi_phy_disable,
3644 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3645 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3646 .channel_map = vc5_hdmi_channel_map,
3647 .supports_hdr = true,
3648 .hp_detect = vc5_hdmi_hp_detect,
3649 };
3650
3651 static const struct of_device_id vc4_hdmi_dt_match[] = {
3652 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3653 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3654 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3655 {}
3656 };
3657
3658 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3659 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3660 vc4_hdmi_runtime_resume,
3661 NULL)
3662 };
3663
3664 struct platform_driver vc4_hdmi_driver = {
3665 .probe = vc4_hdmi_dev_probe,
3666 .remove = vc4_hdmi_dev_remove,
3667 .driver = {
3668 .name = "vc4_hdmi",
3669 .of_match_table = vc4_hdmi_dt_match,
3670 .pm = &vc4_hdmi_pm_ops,
3671 },
3672 };
3673