Searched refs:AVIVO_D1GRPH_UPDATE (Results 1 – 4 of 4) sorted by relevance
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()129 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()153 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
336 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_stop()339 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_stop()386 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()389 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_resume()397 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
815 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()820 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()843 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()851 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()859 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
419 #define AVIVO_D1GRPH_UPDATE 0x6144 macro