Searched refs:BB_PLL_CONFIG_OFFSET (Results 1 – 2 of 2) sorted by relevance
| /drivers/net/wireless/ath/ath10k/ | ||
| D | hw.h | 1170 #define BB_PLL_CONFIG_OFFSET 0x000002f4 macro |
| D | hw.c | 772 addr = (RTC_SOC_BASE_ADDRESS | BB_PLL_CONFIG_OFFSET); in ath10k_hw_qca6174_enable_pll_clock() |