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Searched refs:BIT28 (Results 1 – 16 of 16) sorted by relevance

/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_BB.c236 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
270 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
273 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
498 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
531 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
534 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
Dodm_DynamicBBPowerSaving.c70 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); /* Reg818[28]= 1'b0 */ in ODM_RF_Saving()
71 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x1); /* Reg818[28]= 1'b1 */ in ODM_RF_Saving()
77 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); in ODM_RF_Saving()
DHalHWImg8723B_MAC.c206 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
237 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
240 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
DHalHWImg8723B_RF.c237 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
271 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
274 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
DHalPhyRf_8723B.c96 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32); in setIqkMatrix_8723B()
113 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); in setIqkMatrix_8723B()
452 !(regEAC & BIT28) && in phy_PathA_IQK_8723B()
551 !(regEAC & BIT28) && in phy_PathA_RxIQK8723B()
735 !(regEAC & BIT28) && in phy_PathB_IQK_8723B()
830 !(regEAC & BIT28) && in phy_PathB_RxIQK8723B()
DHal8723BReg.h383 #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h59 #define BIT28 0x10000000 macro
/drivers/staging/rtl8723bs/include/
Drtl8723b_spec.h194 #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
Dosdep_service.h45 #define BIT28 0x10000000 macro
Dhal_com_reg.h687 #define IMR_BCNDMAINT3 BIT28 /* Beacon DMA Interrupt 3 */
734 #define RCR_APP_PHYST_RXFF BIT28 /* PHY Status is appended before RX packet in RXFF */
Dhal_intf.h261 #define RF_CHANGE_BY_IPS BIT28
/drivers/staging/rtl8192e/
Drtl819x_Qos.h38 #define BIT28 0x10000000 macro
Drtllib.h1277 #define RF_CHANGE_BY_IPS BIT28
/drivers/scsi/
Ddc395x.h48 #define BIT28 0x10000000 macro
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h210 #define IMR_ATIMEND BIT28
/drivers/scsi/lpfc/
Dlpfc_hw4.h797 #define LPFC_SLI4_INTR28 BIT28