Searched refs:BMC (Results 1 – 25 of 30) sorted by relevance
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74 Provides a driver for a SMBus interface to a BMC, meaning that you83 It supports normal system interface messages to a BMC on the IPMB113 tristate "Aspeed KCS IPMI BMC driver"118 The driver implements the BMC side of the KCS contorller, it119 provides the access of KCS IO space for BMC side.125 tristate "NPCM KCS IPMI BMC driver"130 The driver implements the BMC side of the KCS contorller, it131 provides the access of KCS IO space for BMC side.138 tristate "IPMI character device interface for BMC KCS devices"140 Provides a BMC-side character device implementing IPMI[all …]
14 also provides a read/write interface to a BMC ram region where the24 allows the BMC to listen on and save the data written by38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The53 Say yes to support decoding of ASPEED BMC information.
11 AST2500 and AST2600 SoCs. It allows BMC to discover devices15 as BMC for Intel platform.
14 can only run on a baseboard management controller (BMC) connected to29 can only run on a baseboard management controller (BMC) connected to
3 tristate "ASPEED BMC Display Controller"
10 This driver enables BMC's diagnostic requests and enables
211 the card's BMC (Board Management Controller).248 tristate "Intel MAX10 BMC Secure Update driver"257 (BMC) and provides support for secure updates for the BMC image,
62 #define BMC BIT(7) macro
505 ptxdesc->txdw2 |= cpu_to_le32(BMC); in update_txdesc()542 ptxdesc->txdw2 |= cpu_to_le32(BMC); in update_txdesc()559 ptxdesc->txdw2 |= cpu_to_le32(BMC); in update_txdesc()
10 If you are building a Baseboard Management Controller (BMC) kernel
43 #define BMC BIT(24) macro
140 bool "NPCM BMC Reset Driver" if COMPILE_TEST144 BMC SoCs.220 - ASPEED BMC SoCs
63 Enable it for your BMC kernel in an OpenPower or IBM Power system.
262 bool "Clock driver for Aspeed BMC SoCs"268 This driver supports the SoC clocks on the Aspeed BMC platforms.
522 tristate "Aspeed AST BMC SoC"525 Support for error detection and correction on the Aspeed AST BMC SoC.
27 #define BMC BIT(24) macro
1207 tristate "MEN 14F021P00 BMC Hardware Monitoring"1210 Say Y here to include support for the MEN 14F021P00 BMC1535 If you're not building a kernel for a BMC, this is probably1665 sensors on AMD SoCs with SB-TSI interface connected to a BMC device.1675 sensors on AMD SoCs with APML interface connected to a BMC device.2324 tristate "Intel MAX10 BMC Hardware Monitoring"2328 on Intel MAX10 BMC chip.2330 This BMC Chip is used on Intel FPGA PCIe Acceleration Cards (PAC). Its
173 ptxdesc->txdw0 |= cpu_to_le32(BMC); in update_txdesc()
301 This driver enables the ACPI to access the BMC controller. And it302 uses the IPMI request/response message to communicate with BMC
107 between the OS and a platform such as the BMC. This medium
691 tristate "LED support for the MEN 14F021P00 BMC"694 Say Y here to include support for the MEN 14F021P00 BMC LEDs.
666 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
247 tristate "MEN 14F021P00 BMC Watchdog"252 Say Y here to include support for the MEN 14F021P00 BMC Watchdog.903 tristate "Aspeed BMC watchdog support"908 in Aspeed BMC SoCs.
80 to a SPI slave to Avalon bridge in a Intel MAX BMC.651 This driver provides support for Nuvoton NPCM BMC
261 BMC platforms, enable this option. This enables the 16550A-