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Searched refs:C2_R_Cr (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_formats.c199 C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
205 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
211 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
217 C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
223 C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
229 C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
235 C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
241 C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
247 C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
253 C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
[all …]
Ddpu_hw_mdss.h287 C2_R_Cr = 2, enumerator
Ddpu_hw_wb.c97 (fmt->bits[C2_R_Cr] << 4) | in dpu_hw_wb_setup_format()
Ddpu_hw_intf.c206 (fmt->bits[C2_R_Cr] << 4) | in dpu_hw_intf_setup_timing_engine()
Ddpu_hw_sspp.c285 (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | in dpu_hw_sspp_setup_format()