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Searched refs:CFG_CLE_FPSEL0 (Results 1 – 2 of 2) sorted by relevance

/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h168 #define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16)) macro
Dxgene_enet_sgmac.c503 data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel) | in xgene_enet_cle_bypass()