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Searched refs:CLK_CTL (Results 1 – 8 of 8) sorted by relevance

/drivers/mmc/host/
Drtsx_pci_sdmmc.c623 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK); in sd_change_phase()
636 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); in sd_change_phase()
1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1032 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1056 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1060 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1070 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1074 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
/drivers/misc/cardreader/
Drts5228.c171 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5228_sd_set_sample_push_timing_sd30()
174 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5228_sd_set_sample_push_timing_sd30()
648 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rts5228_pci_switch_clock()
674 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5228_pci_switch_clock()
Drts5261.c148 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5261_sd_set_sample_push_timing_sd30()
151 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_sd_set_sample_push_timing_sd30()
727 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rts5261_pci_switch_clock()
753 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_pci_switch_clock()
Drts5260.c168 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_sample_push_timing_sd30()
171 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_sample_push_timing_sd30()
Drtsx_pcr.c783 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rtsx_pci_switch_clock()
805 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rtsx_pci_switch_clock()
/drivers/staging/rts5208/
Drtsx_card.c665 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in switch_ssc_clock()
683 retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0); in switch_ssc_clock()
778 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); in switch_normal_clock()
811 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0); in switch_normal_clock()
Drtsx_card.h819 #define CLK_CTL 0xFC02 macro
Dsd.c837 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK,
853 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0);
876 retval = rtsx_write_register(chip, CLK_CTL,
915 retval = rtsx_write_register(chip, CLK_CTL,