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Searched refs:CPG_SIPLL5_CLK3 (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/renesas/
Drzg2l-cpg.h14 #define CPG_SIPLL5_CLK3 (0x14C) macro
Drzg2l-cpg.c607 writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3); in rzg2l_cpg_sipll5_set_rate()