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Searched refs:CP_ME2_PIPE0_INT_CNTL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/radeon/
Dcikd.h1362 #define CP_ME2_PIPE0_INT_CNTL 0xC224 macro
Dcik.c6872 WREG32(CP_ME2_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7226 WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0); in cik_irq_set()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c9260 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, in gfx_v10_0_kiq_set_interrupt_state()
9270 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, in gfx_v10_0_kiq_set_interrupt_state()
Dgfx_v8_0.c6587 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()