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Searched refs:CP_MQD_CONTROL (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dmes_v10_1.c662 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v10_1_mqd_init()
757 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
Dmes_v11_0.c730 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_mqd_init()
821 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_queue_init_register()
Dgfx_v9_0.c3345 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v9_0_mqd_init()
Dgfx_v11_0.c3829 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v11_0_compute_mqd_init()
Dgfx_v8_0.c4480 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v8_0_mqd_init()
Dgfx_v10_0.c6723 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v10_0_compute_mqd_init()
/drivers/gpu/drm/radeon/
Dcikd.h1542 #define CP_MQD_CONTROL 0xC99C macro
Dcik.c4646 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL); in cik_cp_compute_resume()
4648 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in cik_cp_compute_resume()