Searched refs:DMA_BUS_MODE (Results 1 – 8 of 8) sorted by relevance
26 ioaddr + DMA_BUS_MODE); in dwmac100_dma_init()73 reg_space[DMA_BUS_MODE / 4 + i] = in dwmac100_dump_dma_regs()74 readl(ioaddr + DMA_BUS_MODE + i * 4); in dwmac100_dump_dma_regs()
76 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac1000_dma_init()107 writel(value, ioaddr + DMA_BUS_MODE); in dwmac1000_dma_init()217 reg_space[DMA_BUS_MODE / 4 + i] = in dwmac1000_dump_dma_regs()218 readl(ioaddr + DMA_BUS_MODE + i * 4); in dwmac1000_dump_dma_regs()
18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()22 writel(value, ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac_dma_reset()
17 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()21 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()23 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac4_dma_reset()
15 #define DMA_BUS_MODE 0x00001000 /* Bus Mode */ macro
165 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_init()175 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_init()
18 #define DMA_BUS_MODE 0x00001000 macro
467 ®_space[DMA_BUS_MODE / 4], in stmmac_ethtool_gregs()