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Searched refs:DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_intel_display.c340 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in psb_intel_crtc_clock_get()
Dpsb_intel_reg.h253 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
Dcdv_intel_display.c873 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in cdv_intel_crtc_clock_get()
/drivers/gpu/drm/i915/
Di915_reg.h1536 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 macro
/drivers/gpu/drm/i915/display/
Dintel_display.c4461 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()