1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 23 ((MINOR & 0xFFF) << 16) |\ 24 (STEP & 0xFFFF)) 25 26 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 27 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 28 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 29 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 30 31 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 32 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 33 34 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 35 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 36 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 37 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 38 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 39 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 40 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 41 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 42 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 43 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 44 #define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ 45 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 46 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 47 #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ 48 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ 49 50 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 51 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 52 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 53 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 54 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 55 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 56 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) 57 58 #define DPU_HW_BLK_NAME_LEN 16 59 60 #define MAX_IMG_WIDTH 0x3fff 61 #define MAX_IMG_HEIGHT 0x3fff 62 63 #define CRTC_DUAL_MIXERS 2 64 65 #define MAX_XIN_COUNT 16 66 67 /** 68 * Supported UBWC feature versions 69 */ 70 enum { 71 DPU_HW_UBWC_VER_10 = 0x100, 72 DPU_HW_UBWC_VER_20 = 0x200, 73 DPU_HW_UBWC_VER_30 = 0x300, 74 DPU_HW_UBWC_VER_40 = 0x400, 75 }; 76 77 /** 78 * MDP TOP BLOCK features 79 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe 80 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 81 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 82 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 83 * compression initial revision 84 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 85 * @DPU_MDP_MAX Maximum value 86 87 */ 88 enum { 89 DPU_MDP_PANIC_PER_PIPE = 0x1, 90 DPU_MDP_10BIT_SUPPORT, 91 DPU_MDP_BWC, 92 DPU_MDP_UBWC_1_0, 93 DPU_MDP_UBWC_1_5, 94 DPU_MDP_AUDIO_SELECT, 95 DPU_MDP_MAX 96 }; 97 98 /** 99 * SSPP sub-blocks/features 100 * @DPU_SSPP_SRC Src and fetch part of the pipes, 101 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 102 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 103 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 104 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 105 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 106 * @DPU_SSPP_CSC, Support of Color space converion 107 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 108 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 109 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 110 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 111 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 112 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 113 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 114 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 115 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 116 * @DPU_SSPP_CDP Supports client driven prefetch 117 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 118 * @DPU_SSPP_MAX maximum value 119 */ 120 enum { 121 DPU_SSPP_SRC = 0x1, 122 DPU_SSPP_SCALER_QSEED2, 123 DPU_SSPP_SCALER_QSEED3, 124 DPU_SSPP_SCALER_QSEED3LITE, 125 DPU_SSPP_SCALER_QSEED4, 126 DPU_SSPP_SCALER_RGB, 127 DPU_SSPP_CSC, 128 DPU_SSPP_CSC_10BIT, 129 DPU_SSPP_CURSOR, 130 DPU_SSPP_QOS, 131 DPU_SSPP_QOS_8LVL, 132 DPU_SSPP_EXCL_RECT, 133 DPU_SSPP_SMART_DMA_V1, 134 DPU_SSPP_SMART_DMA_V2, 135 DPU_SSPP_TS_PREFILL, 136 DPU_SSPP_TS_PREFILL_REC1, 137 DPU_SSPP_CDP, 138 DPU_SSPP_INLINE_ROTATION, 139 DPU_SSPP_MAX 140 }; 141 142 /* 143 * MIXER sub-blocks/features 144 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 145 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 146 * @DPU_MIXER_GC Gamma correction block 147 * @DPU_DIM_LAYER Layer mixer supports dim layer 148 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 149 * @DPU_MIXER_MAX maximum value 150 */ 151 enum { 152 DPU_MIXER_LAYER = 0x1, 153 DPU_MIXER_SOURCESPLIT, 154 DPU_MIXER_GC, 155 DPU_DIM_LAYER, 156 DPU_MIXER_COMBINED_ALPHA, 157 DPU_MIXER_MAX 158 }; 159 160 /** 161 * DSPP sub-blocks 162 * @DPU_DSPP_PCC Panel color correction block 163 * @DPU_DSPP_GC Gamma correction block 164 */ 165 enum { 166 DPU_DSPP_PCC = 0x1, 167 DPU_DSPP_GC, 168 DPU_DSPP_MAX 169 }; 170 171 /** 172 * PINGPONG sub-blocks 173 * @DPU_PINGPONG_TE Tear check block 174 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 175 * @DPU_PINGPONG_SPLIT PP block supports split fifo 176 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 177 * @DPU_PINGPONG_DITHER, Dither blocks 178 * @DPU_PINGPONG_MAX 179 */ 180 enum { 181 DPU_PINGPONG_TE = 0x1, 182 DPU_PINGPONG_TE2, 183 DPU_PINGPONG_SPLIT, 184 DPU_PINGPONG_SLAVE, 185 DPU_PINGPONG_DITHER, 186 DPU_PINGPONG_MAX 187 }; 188 189 /** 190 * CTL sub-blocks 191 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 192 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 193 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 194 * @DPU_CTL_MAX 195 */ 196 enum { 197 DPU_CTL_SPLIT_DISPLAY = 0x1, 198 DPU_CTL_ACTIVE_CFG, 199 DPU_CTL_FETCH_ACTIVE, 200 DPU_CTL_VM_CFG, 201 DPU_CTL_MAX 202 }; 203 204 /** 205 * INTF sub-blocks 206 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 207 * pixel data arrives to this INTF 208 * @DPU_INTF_TE INTF block has TE configuration support 209 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 210 * than video timing 211 * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register 212 * @DPU_INTF_MAX 213 */ 214 enum { 215 DPU_INTF_INPUT_CTRL = 0x1, 216 DPU_INTF_TE, 217 DPU_DATA_HCTL_EN, 218 DPU_INTF_STATUS_SUPPORTED, 219 DPU_INTF_MAX 220 }; 221 222 /** 223 * WB sub-blocks and features 224 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 225 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 226 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 227 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 228 * @DPU_WB_DITHER, Dither block 229 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 230 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 231 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 232 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 233 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 234 * the destination image 235 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 236 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 237 * @DPU_WB_CDP Writeback supports client driven prefetch 238 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 239 * data arrives. 240 * @DPU_WB_CROP CWB supports cropping 241 * @DPU_WB_MAX maximum value 242 */ 243 enum { 244 DPU_WB_LINE_MODE = 0x1, 245 DPU_WB_BLOCK_MODE, 246 DPU_WB_UBWC, 247 DPU_WB_YUV_CONFIG, 248 DPU_WB_PIPE_ALPHA, 249 DPU_WB_XY_ROI_OFFSET, 250 DPU_WB_QOS, 251 DPU_WB_QOS_8LVL, 252 DPU_WB_CDP, 253 DPU_WB_INPUT_CTRL, 254 DPU_WB_CROP, 255 DPU_WB_MAX 256 }; 257 258 /** 259 * VBIF sub-blocks and features 260 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 261 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 262 * @DPU_VBIF_MAX maximum value 263 */ 264 enum { 265 DPU_VBIF_QOS_OTLIM = 0x1, 266 DPU_VBIF_QOS_REMAP, 267 DPU_VBIF_MAX 268 }; 269 270 /** 271 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 272 * @name: string name for debug purposes 273 * @id: enum identifying this block 274 * @base: register base offset to mdss 275 * @len: length of hardware block 276 * @features bit mask identifying sub-blocks/features 277 */ 278 #define DPU_HW_BLK_INFO \ 279 char name[DPU_HW_BLK_NAME_LEN]; \ 280 u32 id; \ 281 u32 base; \ 282 u32 len; \ 283 unsigned long features 284 285 /** 286 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 287 * @name: string name for debug purposes 288 * @id: enum identifying this sub-block 289 * @base: offset of this sub-block relative to the block 290 * offset 291 * @len register block length of this sub-block 292 */ 293 #define DPU_HW_SUBBLK_INFO \ 294 char name[DPU_HW_BLK_NAME_LEN]; \ 295 u32 id; \ 296 u32 base; \ 297 u32 len 298 299 /** 300 * struct dpu_src_blk: SSPP part of the source pipes 301 * @info: HW register and features supported by this sub-blk 302 */ 303 struct dpu_src_blk { 304 DPU_HW_SUBBLK_INFO; 305 }; 306 307 /** 308 * struct dpu_scaler_blk: Scaler information 309 * @info: HW register and features supported by this sub-blk 310 * @version: qseed block revision 311 */ 312 struct dpu_scaler_blk { 313 DPU_HW_SUBBLK_INFO; 314 u32 version; 315 }; 316 317 struct dpu_csc_blk { 318 DPU_HW_SUBBLK_INFO; 319 }; 320 321 /** 322 * struct dpu_pp_blk : Pixel processing sub-blk information 323 * @info: HW register and features supported by this sub-blk 324 * @version: HW Algorithm version 325 */ 326 struct dpu_pp_blk { 327 DPU_HW_SUBBLK_INFO; 328 u32 version; 329 }; 330 331 /** 332 * enum dpu_qos_lut_usage - define QoS LUT use cases 333 */ 334 enum dpu_qos_lut_usage { 335 DPU_QOS_LUT_USAGE_LINEAR, 336 DPU_QOS_LUT_USAGE_MACROTILE, 337 DPU_QOS_LUT_USAGE_NRT, 338 DPU_QOS_LUT_USAGE_MAX, 339 }; 340 341 /** 342 * struct dpu_qos_lut_entry - define QoS LUT table entry 343 * @fl: fill level, or zero on last entry to indicate default lut 344 * @lut: lut to use if equal to or less than fill level 345 */ 346 struct dpu_qos_lut_entry { 347 u32 fl; 348 u64 lut; 349 }; 350 351 /** 352 * struct dpu_qos_lut_tbl - define QoS LUT table 353 * @nentry: number of entry in this table 354 * @entries: Pointer to table entries 355 */ 356 struct dpu_qos_lut_tbl { 357 u32 nentry; 358 const struct dpu_qos_lut_entry *entries; 359 }; 360 361 /** 362 * struct dpu_rotation_cfg - define inline rotation config 363 * @rot_maxheight: max pre rotated height allowed for rotation 364 * @rot_num_formats: number of elements in @rot_format_list 365 * @rot_format_list: list of supported rotator formats 366 */ 367 struct dpu_rotation_cfg { 368 u32 rot_maxheight; 369 size_t rot_num_formats; 370 const u32 *rot_format_list; 371 }; 372 373 /** 374 * struct dpu_caps - define DPU capabilities 375 * @max_mixer_width max layer mixer line width support. 376 * @max_mixer_blendstages max layer mixer blend stages or 377 * supported z order 378 * @qseed_type qseed2 or qseed3 support. 379 * @smart_dma_rev Supported version of SmartDMA feature. 380 * @ubwc_version UBWC feature version (0x0 for not supported) 381 * @has_src_split source split feature status 382 * @has_dim_layer dim layer feature status 383 * @has_idle_pc indicate if idle power collapse feature is supported 384 * @has_3d_merge indicate if 3D merge is supported 385 * @max_linewidth max linewidth for sspp 386 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 387 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 388 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 389 */ 390 struct dpu_caps { 391 u32 max_mixer_width; 392 u32 max_mixer_blendstages; 393 u32 qseed_type; 394 u32 smart_dma_rev; 395 u32 ubwc_version; 396 bool has_src_split; 397 bool has_dim_layer; 398 bool has_idle_pc; 399 bool has_3d_merge; 400 /* SSPP limits */ 401 u32 max_linewidth; 402 u32 pixel_ram_size; 403 u32 max_hdeci_exp; 404 u32 max_vdeci_exp; 405 }; 406 407 /** 408 * struct dpu_sspp_sub_blks : SSPP sub-blocks 409 * common: Pointer to common configurations shared by sub blocks 410 * @creq_vblank: creq priority during vertical blanking 411 * @danger_vblank: danger priority during vertical blanking 412 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 413 * @maxupscale: maxupscale ratio supported 414 * @smart_dma_priority: hw priority of rect1 of multirect pipe 415 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 416 * @qseed_ver: qseed version 417 * @src_blk: 418 * @scaler_blk: 419 * @csc_blk: 420 * @hsic: 421 * @memcolor: 422 * @pcc_blk: 423 * @igc_blk: 424 * @format_list: Pointer to list of supported formats 425 * @num_formats: Number of supported formats 426 * @virt_format_list: Pointer to list of supported formats for virtual planes 427 * @virt_num_formats: Number of supported formats for virtual planes 428 * @dpu_rotation_cfg: inline rotation configuration 429 */ 430 struct dpu_sspp_sub_blks { 431 u32 creq_vblank; 432 u32 danger_vblank; 433 u32 maxdwnscale; 434 u32 maxupscale; 435 u32 smart_dma_priority; 436 u32 max_per_pipe_bw; 437 u32 qseed_ver; 438 struct dpu_src_blk src_blk; 439 struct dpu_scaler_blk scaler_blk; 440 struct dpu_pp_blk csc_blk; 441 struct dpu_pp_blk hsic_blk; 442 struct dpu_pp_blk memcolor_blk; 443 struct dpu_pp_blk pcc_blk; 444 struct dpu_pp_blk igc_blk; 445 446 const u32 *format_list; 447 u32 num_formats; 448 const u32 *virt_format_list; 449 u32 virt_num_formats; 450 const struct dpu_rotation_cfg *rotation_cfg; 451 }; 452 453 /** 454 * struct dpu_lm_sub_blks: information of mixer block 455 * @maxwidth: Max pixel width supported by this mixer 456 * @maxblendstages: Max number of blend-stages supported 457 * @blendstage_base: Blend-stage register base offset 458 * @gc: gamma correction block 459 */ 460 struct dpu_lm_sub_blks { 461 u32 maxwidth; 462 u32 maxblendstages; 463 u32 blendstage_base[MAX_BLOCKS]; 464 struct dpu_pp_blk gc; 465 }; 466 467 /** 468 * struct dpu_dspp_sub_blks: Information of DSPP block 469 * @gc : gamma correction block 470 * @pcc: pixel color correction block 471 */ 472 struct dpu_dspp_sub_blks { 473 struct dpu_pp_blk gc; 474 struct dpu_pp_blk pcc; 475 }; 476 477 struct dpu_pingpong_sub_blks { 478 struct dpu_pp_blk te; 479 struct dpu_pp_blk te2; 480 struct dpu_pp_blk dither; 481 }; 482 483 /** 484 * dpu_clk_ctrl_type - Defines top level clock control signals 485 */ 486 enum dpu_clk_ctrl_type { 487 DPU_CLK_CTRL_NONE, 488 DPU_CLK_CTRL_VIG0, 489 DPU_CLK_CTRL_VIG1, 490 DPU_CLK_CTRL_VIG2, 491 DPU_CLK_CTRL_VIG3, 492 DPU_CLK_CTRL_VIG4, 493 DPU_CLK_CTRL_RGB0, 494 DPU_CLK_CTRL_RGB1, 495 DPU_CLK_CTRL_RGB2, 496 DPU_CLK_CTRL_RGB3, 497 DPU_CLK_CTRL_DMA0, 498 DPU_CLK_CTRL_DMA1, 499 DPU_CLK_CTRL_DMA2, 500 DPU_CLK_CTRL_DMA3, 501 DPU_CLK_CTRL_CURSOR0, 502 DPU_CLK_CTRL_CURSOR1, 503 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 504 DPU_CLK_CTRL_REG_DMA, 505 DPU_CLK_CTRL_WB2, 506 DPU_CLK_CTRL_MAX, 507 }; 508 509 /* struct dpu_clk_ctrl_reg : Clock control register 510 * @reg_off: register offset 511 * @bit_off: bit offset 512 */ 513 struct dpu_clk_ctrl_reg { 514 u32 reg_off; 515 u32 bit_off; 516 }; 517 518 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 519 * @id: index identifying this block 520 * @base: register base offset to mdss 521 * @features bit mask identifying sub-blocks/features 522 * @highest_bank_bit: UBWC parameter 523 * @ubwc_static: ubwc static configuration 524 * @ubwc_swizzle: ubwc default swizzle setting 525 * @clk_ctrls clock control register definition 526 */ 527 struct dpu_mdp_cfg { 528 DPU_HW_BLK_INFO; 529 u32 highest_bank_bit; 530 u32 ubwc_swizzle; 531 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 532 }; 533 534 /* struct dpu_ctl_cfg : MDP CTL instance info 535 * @id: index identifying this block 536 * @base: register base offset to mdss 537 * @features bit mask identifying sub-blocks/features 538 * @intr_start: interrupt index for CTL_START 539 */ 540 struct dpu_ctl_cfg { 541 DPU_HW_BLK_INFO; 542 s32 intr_start; 543 }; 544 545 /** 546 * struct dpu_sspp_cfg - information of source pipes 547 * @id: index identifying this block 548 * @base register offset of this block 549 * @features bit mask identifying sub-blocks/features 550 * @sblk: SSPP sub-blocks information 551 * @xin_id: bus client identifier 552 * @clk_ctrl clock control identifier 553 * @type sspp type identifier 554 */ 555 struct dpu_sspp_cfg { 556 DPU_HW_BLK_INFO; 557 const struct dpu_sspp_sub_blks *sblk; 558 u32 xin_id; 559 enum dpu_clk_ctrl_type clk_ctrl; 560 u32 type; 561 }; 562 563 /** 564 * struct dpu_lm_cfg - information of layer mixer blocks 565 * @id: index identifying this block 566 * @base register offset of this block 567 * @features bit mask identifying sub-blocks/features 568 * @sblk: LM Sub-blocks information 569 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 570 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 571 */ 572 struct dpu_lm_cfg { 573 DPU_HW_BLK_INFO; 574 const struct dpu_lm_sub_blks *sblk; 575 u32 pingpong; 576 u32 dspp; 577 unsigned long lm_pair_mask; 578 }; 579 580 /** 581 * struct dpu_dspp_cfg - information of DSPP blocks 582 * @id enum identifying this block 583 * @base register offset of this block 584 * @features bit mask identifying sub-blocks/features 585 * supported by this block 586 * @sblk sub-blocks information 587 */ 588 struct dpu_dspp_cfg { 589 DPU_HW_BLK_INFO; 590 const struct dpu_dspp_sub_blks *sblk; 591 }; 592 593 /** 594 * struct dpu_pingpong_cfg - information of PING-PONG blocks 595 * @id enum identifying this block 596 * @base register offset of this block 597 * @features bit mask identifying sub-blocks/features 598 * @intr_done: index for PINGPONG done interrupt 599 * @intr_rdptr: index for PINGPONG readpointer done interrupt 600 * @sblk sub-blocks information 601 */ 602 struct dpu_pingpong_cfg { 603 DPU_HW_BLK_INFO; 604 u32 merge_3d; 605 s32 intr_done; 606 s32 intr_rdptr; 607 const struct dpu_pingpong_sub_blks *sblk; 608 }; 609 610 /** 611 * struct dpu_merge_3d_cfg - information of DSPP blocks 612 * @id enum identifying this block 613 * @base register offset of this block 614 * @features bit mask identifying sub-blocks/features 615 * supported by this block 616 * @sblk sub-blocks information 617 */ 618 struct dpu_merge_3d_cfg { 619 DPU_HW_BLK_INFO; 620 const struct dpu_merge_3d_sub_blks *sblk; 621 }; 622 623 /** 624 * struct dpu_dsc_cfg - information of DSC blocks 625 * @id enum identifying this block 626 * @base register offset of this block 627 * @features bit mask identifying sub-blocks/features 628 */ 629 struct dpu_dsc_cfg { 630 DPU_HW_BLK_INFO; 631 }; 632 633 /** 634 * struct dpu_intf_cfg - information of timing engine blocks 635 * @id enum identifying this block 636 * @base register offset of this block 637 * @features bit mask identifying sub-blocks/features 638 * @type: Interface type(DSI, DP, HDMI) 639 * @controller_id: Controller Instance ID in case of multiple of intf type 640 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 641 * @intr_underrun: index for INTF underrun interrupt 642 * @intr_vsync: index for INTF VSYNC interrupt 643 */ 644 struct dpu_intf_cfg { 645 DPU_HW_BLK_INFO; 646 u32 type; /* interface type*/ 647 u32 controller_id; 648 u32 prog_fetch_lines_worst_case; 649 s32 intr_underrun; 650 s32 intr_vsync; 651 }; 652 653 /** 654 * struct dpu_wb_cfg - information of writeback blocks 655 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 656 * @vbif_idx: vbif client index 657 * @maxlinewidth: max line width supported by writeback block 658 * @xin_id: bus client identifier 659 * @intr_wb_done: interrupt index for WB_DONE 660 * @format_list: list of formats supported by this writeback block 661 * @num_formats: number of formats supported by this writeback block 662 * @clk_ctrl: clock control identifier 663 */ 664 struct dpu_wb_cfg { 665 DPU_HW_BLK_INFO; 666 u8 vbif_idx; 667 u32 maxlinewidth; 668 u32 xin_id; 669 s32 intr_wb_done; 670 const u32 *format_list; 671 u32 num_formats; 672 enum dpu_clk_ctrl_type clk_ctrl; 673 }; 674 675 /** 676 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 677 * @pps pixel per seconds 678 * @ot_limit OT limit to use up to specified pixel per second 679 */ 680 struct dpu_vbif_dynamic_ot_cfg { 681 u64 pps; 682 u32 ot_limit; 683 }; 684 685 /** 686 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 687 * @count length of cfg 688 * @cfg pointer to array of configuration settings with 689 * ascending requirements 690 */ 691 struct dpu_vbif_dynamic_ot_tbl { 692 u32 count; 693 const struct dpu_vbif_dynamic_ot_cfg *cfg; 694 }; 695 696 /** 697 * struct dpu_vbif_qos_tbl - QoS priority table 698 * @npriority_lvl num of priority level 699 * @priority_lvl pointer to array of priority level in ascending order 700 */ 701 struct dpu_vbif_qos_tbl { 702 u32 npriority_lvl; 703 const u32 *priority_lvl; 704 }; 705 706 /** 707 * struct dpu_vbif_cfg - information of VBIF blocks 708 * @id enum identifying this block 709 * @base register offset of this block 710 * @features bit mask identifying sub-blocks/features 711 * @ot_rd_limit default OT read limit 712 * @ot_wr_limit default OT write limit 713 * @xin_halt_timeout maximum time (in usec) for xin to halt 714 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 715 * @dynamic_ot_rd_tbl dynamic OT read configuration table 716 * @dynamic_ot_wr_tbl dynamic OT write configuration table 717 * @qos_rt_tbl real-time QoS priority table 718 * @qos_nrt_tbl non-real-time QoS priority table 719 * @memtype_count number of defined memtypes 720 * @memtype array of xin memtype definitions 721 */ 722 struct dpu_vbif_cfg { 723 DPU_HW_BLK_INFO; 724 u32 default_ot_rd_limit; 725 u32 default_ot_wr_limit; 726 u32 xin_halt_timeout; 727 u32 qos_rp_remap_size; 728 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 729 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 730 struct dpu_vbif_qos_tbl qos_rt_tbl; 731 struct dpu_vbif_qos_tbl qos_nrt_tbl; 732 u32 memtype_count; 733 u32 memtype[MAX_XIN_COUNT]; 734 }; 735 /** 736 * struct dpu_reg_dma_cfg - information of lut dma blocks 737 * @id enum identifying this block 738 * @base register offset of this block 739 * @features bit mask identifying sub-blocks/features 740 * @version version of lutdma hw block 741 * @trigger_sel_off offset to trigger select registers of lutdma 742 */ 743 struct dpu_reg_dma_cfg { 744 DPU_HW_BLK_INFO; 745 u32 version; 746 u32 trigger_sel_off; 747 u32 xin_id; 748 enum dpu_clk_ctrl_type clk_ctrl; 749 }; 750 751 /** 752 * Define CDP use cases 753 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 754 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 755 */ 756 enum { 757 DPU_PERF_CDP_USAGE_RT, 758 DPU_PERF_CDP_USAGE_NRT, 759 DPU_PERF_CDP_USAGE_MAX 760 }; 761 762 /** 763 * struct dpu_perf_cdp_cfg - define CDP use case configuration 764 * @rd_enable: true if read pipe CDP is enabled 765 * @wr_enable: true if write pipe CDP is enabled 766 */ 767 struct dpu_perf_cdp_cfg { 768 bool rd_enable; 769 bool wr_enable; 770 }; 771 772 /** 773 * struct dpu_perf_cfg - performance control settings 774 * @max_bw_low low threshold of maximum bandwidth (kbps) 775 * @max_bw_high high threshold of maximum bandwidth (kbps) 776 * @min_core_ib minimum bandwidth for core (kbps) 777 * @min_core_ib minimum mnoc ib vote in kbps 778 * @min_llcc_ib minimum llcc ib vote in kbps 779 * @min_dram_ib minimum dram ib vote in kbps 780 * @undersized_prefill_lines undersized prefill in lines 781 * @xtra_prefill_lines extra prefill latency in lines 782 * @dest_scale_prefill_lines destination scaler latency in lines 783 * @macrotile_perfill_lines macrotile latency in lines 784 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 785 * @linear_prefill_lines linear latency in lines 786 * @downscaling_prefill_lines downscaling latency in lines 787 * @amortizable_theshold minimum y position for traffic shaping prefill 788 * @min_prefill_lines minimum pipeline latency in lines 789 * @clk_inefficiency_factor DPU src clock inefficiency factor 790 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 791 * @safe_lut_tbl: LUT tables for safe signals 792 * @danger_lut_tbl: LUT tables for danger signals 793 * @qos_lut_tbl: LUT tables for QoS signals 794 * @cdp_cfg cdp use case configurations 795 */ 796 struct dpu_perf_cfg { 797 u32 max_bw_low; 798 u32 max_bw_high; 799 u32 min_core_ib; 800 u32 min_llcc_ib; 801 u32 min_dram_ib; 802 u32 undersized_prefill_lines; 803 u32 xtra_prefill_lines; 804 u32 dest_scale_prefill_lines; 805 u32 macrotile_prefill_lines; 806 u32 yuv_nv12_prefill_lines; 807 u32 linear_prefill_lines; 808 u32 downscaling_prefill_lines; 809 u32 amortizable_threshold; 810 u32 min_prefill_lines; 811 u32 clk_inefficiency_factor; 812 u32 bw_inefficiency_factor; 813 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 814 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 815 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 816 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 817 }; 818 819 /** 820 * struct dpu_mdss_cfg - information of MDSS HW 821 * This is the main catalog data structure representing 822 * this HW version. Contains number of instances, 823 * register offsets, capabilities of the all MDSS HW sub-blocks. 824 * 825 * @dma_formats Supported formats for dma pipe 826 * @cursor_formats Supported formats for cursor pipe 827 * @vig_formats Supported formats for vig pipe 828 * @mdss_irqs: Bitmap with the irqs supported by the target 829 */ 830 struct dpu_mdss_cfg { 831 const struct dpu_caps *caps; 832 833 u32 mdp_count; 834 const struct dpu_mdp_cfg *mdp; 835 836 u32 ctl_count; 837 const struct dpu_ctl_cfg *ctl; 838 839 u32 sspp_count; 840 const struct dpu_sspp_cfg *sspp; 841 842 u32 mixer_count; 843 const struct dpu_lm_cfg *mixer; 844 845 u32 pingpong_count; 846 const struct dpu_pingpong_cfg *pingpong; 847 848 u32 merge_3d_count; 849 const struct dpu_merge_3d_cfg *merge_3d; 850 851 u32 dsc_count; 852 struct dpu_dsc_cfg *dsc; 853 854 u32 intf_count; 855 const struct dpu_intf_cfg *intf; 856 857 u32 vbif_count; 858 const struct dpu_vbif_cfg *vbif; 859 860 u32 wb_count; 861 const struct dpu_wb_cfg *wb; 862 863 u32 reg_dma_count; 864 const struct dpu_reg_dma_cfg *dma_cfg; 865 866 u32 ad_count; 867 868 u32 dspp_count; 869 const struct dpu_dspp_cfg *dspp; 870 871 /* Add additional block data structures here */ 872 873 const struct dpu_perf_cfg *perf; 874 const struct dpu_format_extended *dma_formats; 875 const struct dpu_format_extended *cursor_formats; 876 const struct dpu_format_extended *vig_formats; 877 878 unsigned long mdss_irqs; 879 }; 880 881 struct dpu_mdss_hw_cfg_handler { 882 u32 hw_rev; 883 const struct dpu_mdss_cfg *dpu_cfg; 884 }; 885 886 /** 887 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 888 * hardcoded target specific catalog information in config structure 889 * @hw_rev: caller needs provide the hardware revision. 890 * 891 * Return: dpu config structure 892 */ 893 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 894 895 #endif /* _DPU_HW_CATALOG_H */ 896