| /drivers/gpu/drm/display/ |
| D | drm_dp_helper.c | 284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay() argument
325 if (offset < DP_RECEIVER_CAP_SIZE) { in __read_delay()
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay() argument
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay() argument
374 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay() argument
398 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay() argument
769 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_type() argument
786 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_tmds() argument
873 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_downstream_port_count() argument
884 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps() argument
[all …]
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| D | drm_dp_mst_topology.c | 3577 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_mst_cap() argument
4841 seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf); in drm_dp_mst_dump_topology()
5900 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; in drm_dp_mst_dsc_aux_for_port()
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| /drivers/gpu/drm/msm/dp/ |
| D | dp_panel.c | 39 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
40 if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) { in dp_panel_read_dpcd()
60 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
61 if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) { in dp_panel_read_dpcd()
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| D | dp_panel.h | 39 u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
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| /drivers/gpu/drm/rockchip/ |
| D | cdn-dp-core.h | 103 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| D | cdn-dp-core.c | 379 DP_RECEIVER_CAP_SIZE); in cdn_dp_get_sink_capability()
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_encoder.h | 83 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_dp.c | 42 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
495 u8 dpcd[DP_RECEIVER_CAP_SIZE];
753 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in amdgpu_atombios_dp_link_train()
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| D | amdgpu_mode.h | 462 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /drivers/gpu/drm/radeon/ |
| D | atombios_dp.c | 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
545 u8 dpcd[DP_RECEIVER_CAP_SIZE];
841 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()
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| D | radeon_mode.h | 470 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 47 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps() argument
70 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps() argument
106 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr() argument
186 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_init_lttpr_and_dprx_caps()
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| D | intel_display_types.h | 1631 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /drivers/gpu/drm/bridge/analogix/ |
| D | analogix-anx6345.c | 64 u8 dpcd[DP_RECEIVER_CAP_SIZE];
135 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
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| D | analogix-anx78xx.c | 83 u8 dpcd[DP_RECEIVER_CAP_SIZE];
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dp.c | 487 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; in nvkm_dp_read_dpcd_caps()
490 ret = nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, outp->dp.dpcd, DP_RECEIVER_CAP_SIZE); in nvkm_dp_read_dpcd_caps()
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| /drivers/gpu/drm/tegra/ |
| D | dp.c | 172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe()
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| /drivers/gpu/drm/bridge/cadence/ |
| D | cdns-mhdp8546-core.c | 1385 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps() argument
1410 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up()
1426 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
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| /drivers/gpu/drm/bridge/ |
| D | tc358767.c | 274 u8 dpcd[DP_RECEIVER_CAP_SIZE];
736 DP_RECEIVER_CAP_SIZE); in tc_get_display_props()
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| D | ite-it6505.c | 427 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /drivers/gpu/drm/xlnx/ |
| D | zynqmp_dp.c | 318 u8 dpcd[DP_RECEIVER_CAP_SIZE];
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| /drivers/gpu/drm/mediatek/ |
| D | mtk_dp.c | 105 u8 rx_cap[DP_RECEIVER_CAP_SIZE];
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