1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 31 enum dc_lane_count { 32 LANE_COUNT_UNKNOWN = 0, 33 LANE_COUNT_ONE = 1, 34 LANE_COUNT_TWO = 2, 35 LANE_COUNT_FOUR = 4, 36 LANE_COUNT_EIGHT = 8, 37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38 }; 39 40 /* This is actually a reference clock (27MHz) multiplier 41 * 162MBps bandwidth for 1.62GHz like rate, 42 * 270MBps for 2.70GHz, 43 * 324MBps for 3.24Ghz, 44 * 540MBps for 5.40GHz 45 * 810MBps for 8.10GHz 46 */ 47 enum dc_link_rate { 48 LINK_RATE_UNKNOWN = 0, 49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane 54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane 56 LINK_RATE_HIGH3 = 0x1E, // Rate_8 (HBR3)- 8.10 Gbps/Lane 57 /* Starting from DP2.0 link rate enum directly represents actual 58 * link rate value in unit of 10 mbps 59 */ 60 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 61 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 62 LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane 63 }; 64 65 enum dc_link_spread { 66 LINK_SPREAD_DISABLED = 0x00, 67 /* 0.5 % downspread 30 kHz */ 68 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 69 /* 0.5 % downspread 33 kHz */ 70 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 71 }; 72 73 enum dc_voltage_swing { 74 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 75 VOLTAGE_SWING_LEVEL1, 76 VOLTAGE_SWING_LEVEL2, 77 VOLTAGE_SWING_LEVEL3, 78 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 79 }; 80 81 enum dc_pre_emphasis { 82 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 83 PRE_EMPHASIS_LEVEL1, 84 PRE_EMPHASIS_LEVEL2, 85 PRE_EMPHASIS_LEVEL3, 86 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 87 }; 88 /* Post Cursor 2 is optional for transmitter 89 * and it applies only to the main link operating at HBR2 90 */ 91 enum dc_post_cursor2 { 92 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 93 POST_CURSOR2_LEVEL1, 94 POST_CURSOR2_LEVEL2, 95 POST_CURSOR2_LEVEL3, 96 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 97 }; 98 99 enum dc_dp_ffe_preset_level { 100 DP_FFE_PRESET_LEVEL0 = 0, 101 DP_FFE_PRESET_LEVEL1, 102 DP_FFE_PRESET_LEVEL2, 103 DP_FFE_PRESET_LEVEL3, 104 DP_FFE_PRESET_LEVEL4, 105 DP_FFE_PRESET_LEVEL5, 106 DP_FFE_PRESET_LEVEL6, 107 DP_FFE_PRESET_LEVEL7, 108 DP_FFE_PRESET_LEVEL8, 109 DP_FFE_PRESET_LEVEL9, 110 DP_FFE_PRESET_LEVEL10, 111 DP_FFE_PRESET_LEVEL11, 112 DP_FFE_PRESET_LEVEL12, 113 DP_FFE_PRESET_LEVEL13, 114 DP_FFE_PRESET_LEVEL14, 115 DP_FFE_PRESET_LEVEL15, 116 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 117 }; 118 119 enum dc_dp_training_pattern { 120 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 121 DP_TRAINING_PATTERN_SEQUENCE_2, 122 DP_TRAINING_PATTERN_SEQUENCE_3, 123 DP_TRAINING_PATTERN_SEQUENCE_4, 124 DP_TRAINING_PATTERN_VIDEOIDLE, 125 DP_128b_132b_TPS1, 126 DP_128b_132b_TPS2, 127 DP_128b_132b_TPS2_CDS, 128 }; 129 130 enum dp_link_encoding { 131 DP_UNKNOWN_ENCODING = 0, 132 DP_8b_10b_ENCODING = 1, 133 DP_128b_132b_ENCODING = 2, 134 }; 135 136 enum dp_test_link_rate { 137 DP_TEST_LINK_RATE_RBR = 0x06, 138 DP_TEST_LINK_RATE_HBR = 0x0A, 139 DP_TEST_LINK_RATE_HBR2 = 0x14, 140 DP_TEST_LINK_RATE_HBR3 = 0x1E, 141 DP_TEST_LINK_RATE_UHBR10 = 0x01, 142 DP_TEST_LINK_RATE_UHBR20 = 0x02, 143 DP_TEST_LINK_RATE_UHBR13_5 = 0x03, 144 }; 145 146 struct dc_link_settings { 147 enum dc_lane_count lane_count; 148 enum dc_link_rate link_rate; 149 enum dc_link_spread link_spread; 150 bool use_link_rate_set; 151 uint8_t link_rate_set; 152 }; 153 154 union dc_dp_ffe_preset { 155 struct { 156 uint8_t level : 4; 157 uint8_t reserved : 1; 158 uint8_t no_preshoot : 1; 159 uint8_t no_deemphasis : 1; 160 uint8_t method2 : 1; 161 } settings; 162 uint8_t raw; 163 }; 164 165 struct dc_lane_settings { 166 enum dc_voltage_swing VOLTAGE_SWING; 167 enum dc_pre_emphasis PRE_EMPHASIS; 168 enum dc_post_cursor2 POST_CURSOR2; 169 union dc_dp_ffe_preset FFE_PRESET; 170 }; 171 172 struct dc_link_training_overrides { 173 enum dc_voltage_swing *voltage_swing; 174 enum dc_pre_emphasis *pre_emphasis; 175 enum dc_post_cursor2 *post_cursor2; 176 union dc_dp_ffe_preset *ffe_preset; 177 178 uint16_t *cr_pattern_time; 179 uint16_t *eq_pattern_time; 180 enum dc_dp_training_pattern *pattern_for_cr; 181 enum dc_dp_training_pattern *pattern_for_eq; 182 183 enum dc_link_spread *downspread; 184 bool *alternate_scrambler_reset; 185 bool *enhanced_framing; 186 bool *mst_enable; 187 bool *fec_enable; 188 }; 189 190 union payload_table_update_status { 191 struct { 192 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 193 uint8_t ACT_HANDLED:1; 194 } bits; 195 uint8_t raw; 196 }; 197 198 union dpcd_rev { 199 struct { 200 uint8_t MINOR:4; 201 uint8_t MAJOR:4; 202 } bits; 203 uint8_t raw; 204 }; 205 206 union max_lane_count { 207 struct { 208 uint8_t MAX_LANE_COUNT:5; 209 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 210 uint8_t TPS3_SUPPORTED:1; 211 uint8_t ENHANCED_FRAME_CAP:1; 212 } bits; 213 uint8_t raw; 214 }; 215 216 union max_down_spread { 217 struct { 218 uint8_t MAX_DOWN_SPREAD:1; 219 uint8_t RESERVED:5; 220 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 221 uint8_t TPS4_SUPPORTED:1; 222 } bits; 223 uint8_t raw; 224 }; 225 226 union mstm_cap { 227 struct { 228 uint8_t MST_CAP:1; 229 uint8_t RESERVED:7; 230 } bits; 231 uint8_t raw; 232 }; 233 234 union lane_count_set { 235 struct { 236 uint8_t LANE_COUNT_SET:5; 237 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 238 uint8_t RESERVED:1; 239 uint8_t ENHANCED_FRAMING:1; 240 } bits; 241 uint8_t raw; 242 }; 243 244 union lane_status { 245 struct { 246 uint8_t CR_DONE_0:1; 247 uint8_t CHANNEL_EQ_DONE_0:1; 248 uint8_t SYMBOL_LOCKED_0:1; 249 uint8_t RESERVED0:1; 250 uint8_t CR_DONE_1:1; 251 uint8_t CHANNEL_EQ_DONE_1:1; 252 uint8_t SYMBOL_LOCKED_1:1; 253 uint8_t RESERVED_1:1; 254 } bits; 255 uint8_t raw; 256 }; 257 258 union device_service_irq { 259 struct { 260 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 261 uint8_t AUTOMATED_TEST:1; 262 uint8_t CP_IRQ:1; 263 uint8_t MCCS_IRQ:1; 264 uint8_t DOWN_REP_MSG_RDY:1; 265 uint8_t UP_REQ_MSG_RDY:1; 266 uint8_t SINK_SPECIFIC:1; 267 uint8_t reserved:1; 268 } bits; 269 uint8_t raw; 270 }; 271 272 union sink_count { 273 struct { 274 uint8_t SINK_COUNT:6; 275 uint8_t CPREADY:1; 276 uint8_t RESERVED:1; 277 } bits; 278 uint8_t raw; 279 }; 280 281 union lane_align_status_updated { 282 struct { 283 uint8_t INTERLANE_ALIGN_DONE:1; 284 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 285 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 286 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 287 uint8_t LT_FAILED_128b_132b:1; 288 uint8_t RESERVED:1; 289 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 290 uint8_t LINK_STATUS_UPDATED:1; 291 } bits; 292 uint8_t raw; 293 }; 294 295 union lane_adjust { 296 struct { 297 uint8_t VOLTAGE_SWING_LANE:2; 298 uint8_t PRE_EMPHASIS_LANE:2; 299 uint8_t RESERVED:4; 300 } bits; 301 struct { 302 uint8_t PRESET_VALUE :4; 303 uint8_t RESERVED :4; 304 } tx_ffe; 305 uint8_t raw; 306 }; 307 308 union dpcd_training_pattern { 309 struct { 310 uint8_t TRAINING_PATTERN_SET:4; 311 uint8_t RECOVERED_CLOCK_OUT_EN:1; 312 uint8_t SCRAMBLING_DISABLE:1; 313 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 314 } v1_4; 315 struct { 316 uint8_t TRAINING_PATTERN_SET:2; 317 uint8_t LINK_QUAL_PATTERN_SET:2; 318 uint8_t RESERVED:4; 319 } v1_3; 320 uint8_t raw; 321 }; 322 323 /* Training Lane is used to configure downstream DP device's voltage swing 324 and pre-emphasis levels*/ 325 /* The DPCD addresses are from 0x103 to 0x106*/ 326 union dpcd_training_lane { 327 struct { 328 uint8_t VOLTAGE_SWING_SET:2; 329 uint8_t MAX_SWING_REACHED:1; 330 uint8_t PRE_EMPHASIS_SET:2; 331 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 332 uint8_t RESERVED:2; 333 } bits; 334 struct { 335 uint8_t PRESET_VALUE :4; 336 uint8_t RESERVED :4; 337 } tx_ffe; 338 uint8_t raw; 339 }; 340 341 /* TMDS-converter related */ 342 union dwnstream_port_caps_byte0 { 343 struct { 344 uint8_t DWN_STRM_PORTX_TYPE:3; 345 uint8_t DWN_STRM_PORTX_HPD:1; 346 uint8_t RESERVERD:4; 347 } bits; 348 uint8_t raw; 349 }; 350 351 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 352 enum dpcd_downstream_port_detailed_type { 353 DOWN_STREAM_DETAILED_DP = 0, 354 DOWN_STREAM_DETAILED_VGA, 355 DOWN_STREAM_DETAILED_DVI, 356 DOWN_STREAM_DETAILED_HDMI, 357 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 358 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 359 }; 360 361 union dwnstream_port_caps_byte2 { 362 struct { 363 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 364 #if defined(CONFIG_DRM_AMD_DC_DCN) 365 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 366 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 367 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 368 uint8_t RESERVED:1; 369 #else 370 uint8_t RESERVED:6; 371 #endif 372 } bits; 373 uint8_t raw; 374 }; 375 376 union dp_downstream_port_present { 377 uint8_t byte; 378 struct { 379 uint8_t PORT_PRESENT:1; 380 uint8_t PORT_TYPE:2; 381 uint8_t FMT_CONVERSION:1; 382 uint8_t DETAILED_CAPS:1; 383 uint8_t RESERVED:3; 384 } fields; 385 }; 386 387 union dwnstream_port_caps_byte3_dvi { 388 struct { 389 uint8_t RESERVED1:1; 390 uint8_t DUAL_LINK:1; 391 uint8_t HIGH_COLOR_DEPTH:1; 392 uint8_t RESERVED2:5; 393 } bits; 394 uint8_t raw; 395 }; 396 397 union dwnstream_port_caps_byte3_hdmi { 398 struct { 399 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 400 uint8_t YCrCr422_PASS_THROUGH:1; 401 uint8_t YCrCr420_PASS_THROUGH:1; 402 uint8_t YCrCr422_CONVERSION:1; 403 uint8_t YCrCr420_CONVERSION:1; 404 uint8_t RESERVED:3; 405 } bits; 406 uint8_t raw; 407 }; 408 409 #if defined(CONFIG_DRM_AMD_DC_DCN) 410 union hdmi_sink_encoded_link_bw_support { 411 struct { 412 uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3; 413 uint8_t RESERVED:5; 414 } bits; 415 uint8_t raw; 416 }; 417 418 union hdmi_encoded_link_bw { 419 struct { 420 uint8_t FRL_MODE:1; // Bit 0 421 uint8_t BW_9Gbps:1; 422 uint8_t BW_18Gbps:1; 423 uint8_t BW_24Gbps:1; 424 uint8_t BW_32Gbps:1; 425 uint8_t BW_40Gbps:1; 426 uint8_t BW_48Gbps:1; 427 uint8_t RESERVED:1; // Bit 7 428 } bits; 429 uint8_t raw; 430 }; 431 #endif 432 433 /*4-byte structure for detailed capabilities of a down-stream port 434 (DP-to-TMDS converter).*/ 435 union dwnstream_portxcaps { 436 struct { 437 union dwnstream_port_caps_byte0 byte0; 438 unsigned char max_TMDS_clock; //byte1 439 union dwnstream_port_caps_byte2 byte2; 440 441 union { 442 union dwnstream_port_caps_byte3_dvi byteDVI; 443 union dwnstream_port_caps_byte3_hdmi byteHDMI; 444 } byte3; 445 } bytes; 446 447 unsigned char raw[4]; 448 }; 449 450 union downstream_port { 451 struct { 452 unsigned char present:1; 453 unsigned char type:2; 454 unsigned char format_conv:1; 455 unsigned char detailed_caps:1; 456 unsigned char reserved:3; 457 } bits; 458 unsigned char raw; 459 }; 460 461 462 union sink_status { 463 struct { 464 uint8_t RX_PORT0_STATUS:1; 465 uint8_t RX_PORT1_STATUS:1; 466 uint8_t RESERVED:6; 467 } bits; 468 uint8_t raw; 469 }; 470 471 /*6-byte structure corresponding to 6 registers (200h-205h) 472 read during handling of HPD-IRQ*/ 473 union hpd_irq_data { 474 struct { 475 union sink_count sink_cnt;/* 200h */ 476 union device_service_irq device_service_irq;/* 201h */ 477 union lane_status lane01_status;/* 202h */ 478 union lane_status lane23_status;/* 203h */ 479 union lane_align_status_updated lane_status_updated;/* 204h */ 480 union sink_status sink_status; 481 } bytes; 482 uint8_t raw[6]; 483 }; 484 485 union down_stream_port_count { 486 struct { 487 uint8_t DOWN_STR_PORT_COUNT:4; 488 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 489 /*Bit 6 = MSA_TIMING_PAR_IGNORED 490 0 = Sink device requires the MSA timing parameters 491 1 = Sink device is capable of rendering incoming video 492 stream without MSA timing parameters*/ 493 uint8_t IGNORE_MSA_TIMING_PARAM:1; 494 /*Bit 7 = OUI Support 495 0 = OUI not supported 496 1 = OUI supported 497 (OUI and Device Identification mandatory for DP 1.2)*/ 498 uint8_t OUI_SUPPORT:1; 499 } bits; 500 uint8_t raw; 501 }; 502 503 union down_spread_ctrl { 504 struct { 505 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 506 /* Bits 4 = SPREAD_AMP. Spreading amplitude 507 0 = Main link signal is not downspread 508 1 = Main link signal is downspread <= 0.5% 509 with frequency in the range of 30kHz ~ 33kHz*/ 510 uint8_t SPREAD_AMP:1; 511 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 512 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 513 0 = Source device will send valid data for the MSA Timing Params 514 1 = Source device may send invalid data for these MSA Timing Params*/ 515 uint8_t IGNORE_MSA_TIMING_PARAM:1; 516 } bits; 517 uint8_t raw; 518 }; 519 520 union dpcd_edp_config { 521 struct { 522 uint8_t PANEL_MODE_EDP:1; 523 uint8_t FRAMING_CHANGE_ENABLE:1; 524 uint8_t RESERVED:5; 525 uint8_t PANEL_SELF_TEST_ENABLE:1; 526 } bits; 527 uint8_t raw; 528 }; 529 530 struct dp_device_vendor_id { 531 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 532 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 533 }; 534 535 struct dp_sink_hw_fw_revision { 536 uint8_t ieee_hw_rev; 537 uint8_t ieee_fw_rev[2]; 538 }; 539 540 struct dpcd_vendor_signature { 541 bool is_valid; 542 543 union dpcd_ieee_vendor_signature { 544 struct { 545 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 546 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 547 uint8_t ieee_hw_rev; 548 uint8_t ieee_fw_rev[2]; 549 }; 550 uint8_t raw[12]; 551 } data; 552 }; 553 554 struct dpcd_amd_signature { 555 uint8_t AMD_IEEE_TxSignature_byte1; 556 uint8_t AMD_IEEE_TxSignature_byte2; 557 uint8_t AMD_IEEE_TxSignature_byte3; 558 }; 559 560 struct dpcd_amd_device_id { 561 uint8_t device_id_byte1; 562 uint8_t device_id_byte2; 563 uint8_t zero[4]; 564 uint8_t dce_version; 565 uint8_t dal_version_byte1; 566 uint8_t dal_version_byte2; 567 }; 568 569 struct dpcd_source_backlight_set { 570 struct { 571 uint8_t byte0; 572 uint8_t byte1; 573 uint8_t byte2; 574 uint8_t byte3; 575 } backlight_level_millinits; 576 577 struct { 578 uint8_t byte0; 579 uint8_t byte1; 580 } backlight_transition_time_ms; 581 }; 582 583 union dpcd_source_backlight_get { 584 struct { 585 uint32_t backlight_millinits_peak; /* 326h */ 586 uint32_t backlight_millinits_avg; /* 32Ah */ 587 } bytes; 588 uint8_t raw[8]; 589 }; 590 591 /*DPCD register of DP receiver capability field bits-*/ 592 union edp_configuration_cap { 593 struct { 594 uint8_t ALT_SCRAMBLER_RESET:1; 595 uint8_t FRAMING_CHANGE:1; 596 uint8_t RESERVED:1; 597 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 598 uint8_t RESERVED2:4; 599 } bits; 600 uint8_t raw; 601 }; 602 603 union dprx_feature { 604 struct { 605 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 606 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 607 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 608 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 609 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 610 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 611 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 612 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 613 } bits; 614 uint8_t raw; 615 }; 616 617 union training_aux_rd_interval { 618 struct { 619 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 620 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 621 } bits; 622 uint8_t raw; 623 }; 624 625 /* Automated test structures */ 626 union test_request { 627 struct { 628 uint8_t LINK_TRAINING :1; 629 uint8_t LINK_TEST_PATTRN :1; 630 uint8_t EDID_READ :1; 631 uint8_t PHY_TEST_PATTERN :1; 632 uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2; 633 uint8_t AUDIO_TEST_PATTERN :1; 634 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 635 } bits; 636 uint8_t raw; 637 }; 638 639 union test_response { 640 struct { 641 uint8_t ACK :1; 642 uint8_t NO_ACK :1; 643 uint8_t EDID_CHECKSUM_WRITE:1; 644 uint8_t RESERVED :5; 645 } bits; 646 uint8_t raw; 647 }; 648 649 union phy_test_pattern { 650 struct { 651 /* This field is 7 bits for DP2.0 */ 652 uint8_t PATTERN :7; 653 uint8_t RESERVED :1; 654 } bits; 655 uint8_t raw; 656 }; 657 658 /* States of Compliance Test Specification (CTS DP1.2). */ 659 union compliance_test_state { 660 struct { 661 unsigned char STEREO_3D_RUNNING : 1; 662 unsigned char RESERVED : 7; 663 } bits; 664 unsigned char raw; 665 }; 666 667 union link_test_pattern { 668 struct { 669 /* dpcd_link_test_patterns */ 670 unsigned char PATTERN :2; 671 unsigned char RESERVED:6; 672 } bits; 673 unsigned char raw; 674 }; 675 676 union test_misc { 677 struct dpcd_test_misc_bits { 678 unsigned char SYNC_CLOCK :1; 679 /* dpcd_test_color_format */ 680 unsigned char CLR_FORMAT :2; 681 /* dpcd_test_dyn_range */ 682 unsigned char DYN_RANGE :1; 683 unsigned char YCBCR_COEFS :1; 684 /* dpcd_test_bit_depth */ 685 unsigned char BPC :3; 686 } bits; 687 unsigned char raw; 688 }; 689 690 union audio_test_mode { 691 struct { 692 unsigned char sampling_rate :4; 693 unsigned char channel_count :4; 694 } bits; 695 unsigned char raw; 696 }; 697 698 union audio_test_pattern_period { 699 struct { 700 unsigned char pattern_period :4; 701 unsigned char reserved :4; 702 } bits; 703 unsigned char raw; 704 }; 705 706 struct audio_test_pattern_type { 707 unsigned char value; 708 }; 709 710 struct dp_audio_test_data_flags { 711 uint8_t test_requested :1; 712 uint8_t disable_video :1; 713 }; 714 715 struct dp_audio_test_data { 716 717 struct dp_audio_test_data_flags flags; 718 uint8_t sampling_rate; 719 uint8_t channel_count; 720 uint8_t pattern_type; 721 uint8_t pattern_period[8]; 722 }; 723 724 /* FEC capability DPCD register field bits-*/ 725 union dpcd_fec_capability { 726 struct { 727 uint8_t FEC_CAPABLE:1; 728 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 729 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 730 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 731 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 732 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 733 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 734 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 735 } bits; 736 uint8_t raw; 737 }; 738 739 /* DSC capability DPCD register field bits-*/ 740 struct dpcd_dsc_support { 741 uint8_t DSC_SUPPORT :1; 742 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 743 uint8_t RESERVED :6; 744 }; 745 746 struct dpcd_dsc_algorithm_revision { 747 uint8_t DSC_VERSION_MAJOR :4; 748 uint8_t DSC_VERSION_MINOR :4; 749 }; 750 751 struct dpcd_dsc_rc_buffer_block_size { 752 uint8_t RC_BLOCK_BUFFER_SIZE :2; 753 uint8_t RESERVED :6; 754 }; 755 756 struct dpcd_dsc_slice_capability1 { 757 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 758 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 759 uint8_t RESERVED :1; 760 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 761 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 762 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 763 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 764 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 765 }; 766 767 struct dpcd_dsc_line_buffer_bit_depth { 768 uint8_t LINE_BUFFER_BIT_DEPTH :4; 769 uint8_t RESERVED :4; 770 }; 771 772 struct dpcd_dsc_block_prediction_support { 773 uint8_t BLOCK_PREDICTION_SUPPORT:1; 774 uint8_t RESERVED :7; 775 }; 776 777 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 778 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 779 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 780 uint8_t RESERVED :2; 781 }; 782 783 struct dpcd_dsc_decoder_color_format_capabilities { 784 uint8_t RGB_SUPPORT :1; 785 uint8_t Y_CB_CR_444_SUPPORT :1; 786 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 787 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 788 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 789 uint8_t RESERVED :3; 790 }; 791 792 struct dpcd_dsc_decoder_color_depth_capabilities { 793 uint8_t RESERVED0 :1; 794 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 795 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 796 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 797 uint8_t RESERVED1 :4; 798 }; 799 800 struct dpcd_peak_dsc_throughput_dsc_sink { 801 uint8_t THROUGHPUT_MODE_0:4; 802 uint8_t THROUGHPUT_MODE_1:4; 803 }; 804 805 struct dpcd_dsc_slice_capabilities_2 { 806 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 807 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 808 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 809 uint8_t RESERVED :5; 810 }; 811 812 struct dpcd_bits_per_pixel_increment{ 813 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 814 uint8_t RESERVED :5; 815 }; 816 union dpcd_dsc_basic_capabilities { 817 struct { 818 struct dpcd_dsc_support dsc_support; 819 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 820 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 821 uint8_t dsc_rc_buffer_size; 822 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 823 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 824 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 825 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 826 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 827 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 828 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 829 uint8_t dsc_maximum_slice_width; 830 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 831 uint8_t reserved; 832 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 833 } fields; 834 uint8_t raw[16]; 835 }; 836 837 union dpcd_dsc_branch_decoder_capabilities { 838 struct { 839 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 840 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 841 uint8_t BRANCH_MAX_LINE_WIDTH; 842 } fields; 843 uint8_t raw[3]; 844 }; 845 846 struct dpcd_dsc_capabilities { 847 union dpcd_dsc_basic_capabilities dsc_basic_caps; 848 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 849 }; 850 851 /* These parameters are from PSR capabilities reported by Sink DPCD */ 852 struct psr_caps { 853 unsigned char psr_version; 854 unsigned int psr_rfb_setup_time; 855 bool psr_exit_link_training_required; 856 unsigned char edp_revision; 857 unsigned char support_ver; 858 bool su_granularity_required; 859 bool y_coordinate_required; 860 uint8_t su_y_granularity; 861 bool alpm_cap; 862 bool standby_support; 863 uint8_t rate_control_caps; 864 unsigned int psr_power_opt_flag; 865 }; 866 867 /* Length of router topology ID read from DPCD in bytes. */ 868 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 869 870 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 871 union dp_tun_cap_support { 872 struct { 873 uint8_t dp_tunneling :1; 874 uint8_t rsvd :5; 875 uint8_t panel_replay_tun_opt :1; 876 uint8_t dpia_bw_alloc :1; 877 } bits; 878 uint8_t raw; 879 }; 880 881 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 882 union dpia_info { 883 struct { 884 uint8_t dpia_num :5; 885 uint8_t rsvd :3; 886 } bits; 887 uint8_t raw; 888 }; 889 890 /* DP Tunneling over USB4 */ 891 struct dpcd_usb4_dp_tunneling_info { 892 union dp_tun_cap_support dp_tun_cap; 893 union dpia_info dpia_info; 894 uint8_t usb4_driver_id; 895 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 896 }; 897 898 #ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP 899 #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 900 #endif 901 #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS 902 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 903 #endif 904 #ifndef DP_FEC_CAPABILITY_1 905 #define DP_FEC_CAPABILITY_1 0x091 906 #endif 907 #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT 908 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 909 #endif 910 #ifndef DP_LINK_SQUARE_PATTERN 911 #define DP_LINK_SQUARE_PATTERN 0x10F 912 #endif 913 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 914 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 915 #endif 916 #ifndef DP_DSC_CONFIGURATION 917 #define DP_DSC_CONFIGURATION 0x161 918 #endif 919 #ifndef DP_PHY_SQUARE_PATTERN 920 #define DP_PHY_SQUARE_PATTERN 0x249 921 #endif 922 #ifndef DP_128b_132b_SUPPORTED_LINK_RATES 923 #define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215 924 #endif 925 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL 926 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216 927 #endif 928 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 929 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217 930 #endif 931 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 932 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 933 #endif 934 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 935 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 936 #endif 937 #ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT 938 #define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 939 #endif 940 #ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 941 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 942 #endif 943 #ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK 944 #define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) 945 #endif 946 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK 947 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) 948 #endif 949 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 950 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 951 #endif 952 #ifndef DP_DSC_DECODER_COUNT_MASK 953 #define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) 954 #endif 955 #ifndef DP_DSC_DECODER_COUNT_SHIFT 956 #define DP_DSC_DECODER_COUNT_SHIFT 5 957 #endif 958 #ifndef DP_MAIN_LINK_CHANNEL_CODING_SET 959 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 960 #endif 961 #ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 962 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 963 #endif 964 #ifndef DP_PHY_REPEATER_128b_132b_RATES 965 #define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 966 #endif 967 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 968 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 969 #endif 970 #ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION 971 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) 972 /* TODO - Use DRM header to replace above once available */ 973 #endif // DP_INTRA_HOP_AUX_REPLY_INDICATION 974 975 union dp_main_line_channel_coding_cap { 976 struct { 977 uint8_t DP_8b_10b_SUPPORTED :1; 978 uint8_t DP_128b_132b_SUPPORTED :1; 979 uint8_t RESERVED :6; 980 } bits; 981 uint8_t raw; 982 }; 983 984 union dp_main_link_channel_coding_lttpr_cap { 985 struct { 986 uint8_t DP_128b_132b_SUPPORTED :1; 987 uint8_t RESERVED :7; 988 } bits; 989 uint8_t raw; 990 }; 991 992 union dp_128b_132b_supported_link_rates { 993 struct { 994 uint8_t UHBR10 :1; 995 uint8_t UHBR20 :1; 996 uint8_t UHBR13_5:1; 997 uint8_t RESERVED:5; 998 } bits; 999 uint8_t raw; 1000 }; 1001 1002 union dp_128b_132b_supported_lttpr_link_rates { 1003 struct { 1004 uint8_t UHBR10 :1; 1005 uint8_t UHBR20 :1; 1006 uint8_t UHBR13_5:1; 1007 uint8_t RESERVED:5; 1008 } bits; 1009 uint8_t raw; 1010 }; 1011 1012 union dp_sink_video_fallback_formats { 1013 struct { 1014 uint8_t dp_1024x768_60Hz_24bpp_support :1; 1015 uint8_t dp_1280x720_60Hz_24bpp_support :1; 1016 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 1017 uint8_t RESERVED :5; 1018 } bits; 1019 uint8_t raw; 1020 }; 1021 1022 union dp_fec_capability1 { 1023 struct { 1024 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 1025 uint8_t RESERVED :7; 1026 } bits; 1027 uint8_t raw; 1028 }; 1029 1030 union dp_cable_id { 1031 struct { 1032 uint8_t UHBR10_20_CAPABILITY :2; 1033 uint8_t UHBR13_5_CAPABILITY :1; 1034 uint8_t CABLE_TYPE :3; 1035 uint8_t RESERVED :2; 1036 } bits; 1037 uint8_t raw; 1038 }; 1039 1040 struct dp_color_depth_caps { 1041 uint8_t support_6bpc :1; 1042 uint8_t support_8bpc :1; 1043 uint8_t support_10bpc :1; 1044 uint8_t support_12bpc :1; 1045 uint8_t support_16bpc :1; 1046 uint8_t RESERVED :3; 1047 }; 1048 1049 struct dp_encoding_format_caps { 1050 uint8_t support_rgb :1; 1051 uint8_t support_ycbcr444:1; 1052 uint8_t support_ycbcr422:1; 1053 uint8_t support_ycbcr420:1; 1054 uint8_t RESERVED :4; 1055 }; 1056 1057 union dp_dfp_cap_ext { 1058 struct { 1059 uint8_t supported; 1060 uint8_t max_pixel_rate_in_mps[2]; 1061 uint8_t max_video_h_active_width[2]; 1062 uint8_t max_video_v_active_height[2]; 1063 struct dp_encoding_format_caps encoding_format_caps; 1064 struct dp_color_depth_caps rgb_color_depth_caps; 1065 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1066 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1067 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1068 } fields; 1069 uint8_t raw[12]; 1070 }; 1071 1072 union dp_128b_132b_training_aux_rd_interval { 1073 struct { 1074 uint8_t VALUE :7; 1075 uint8_t UNIT :1; 1076 } bits; 1077 uint8_t raw; 1078 }; 1079 1080 union edp_alpm_caps { 1081 struct { 1082 uint8_t AUX_WAKE_ALPM_CAP :1; 1083 uint8_t PM_STATE_2A_SUPPORT :1; 1084 uint8_t AUX_LESS_ALPM_CAP :1; 1085 uint8_t RESERVED :5; 1086 } bits; 1087 uint8_t raw; 1088 }; 1089 1090 union edp_psr_dpcd_caps { 1091 struct { 1092 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1; 1093 uint8_t PSR_SETUP_TIME :3; 1094 uint8_t Y_COORDINATE_REQUIRED :1; 1095 uint8_t SU_GRANULARITY_REQUIRED :1; 1096 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1; 1097 uint8_t RESERVED :1; 1098 } bits; 1099 uint8_t raw; 1100 }; 1101 1102 struct edp_psr_info { 1103 uint8_t psr_version; 1104 union edp_psr_dpcd_caps psr_dpcd_caps; 1105 uint8_t psr2_su_y_granularity_cap; 1106 uint8_t force_psrsu_cap; 1107 }; 1108 1109 #endif /* DC_DP_TYPES_H */ 1110