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Searched refs:FMT_CONTROL (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_opp.h46 SRI(FMT_CONTROL, FMT, id), \
88 SRI(FMT_CONTROL, FMT, id), \
121 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
130 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
131 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
132 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
136 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
137 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
138 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
142 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
[all …]
Ddce_opp.c227 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
231 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
237 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
476 REG_UPDATE_3(FMT_CONTROL, in set_pixel_encoding()
481 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
486 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
491 REG_UPDATE_3(FMT_CONTROL, in set_pixel_encoding()
512 REG_UPDATE_2(FMT_CONTROL, in dce60_set_pixel_encoding()
516 REG_UPDATE(FMT_CONTROL, in dce60_set_pixel_encoding()
520 REG_UPDATE(FMT_CONTROL, in dce60_set_pixel_encoding()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_opp.c77 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
81 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
88 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
166 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); in opp1_set_pixel_encoding()
169 REG_UPDATE_3(FMT_CONTROL, in opp1_set_pixel_encoding()
175 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); in opp1_set_pixel_encoding()
324 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0); in opp1_program_stereo()
Ddcn10_opp.h38 SRI(FMT_CONTROL, FMT, id), \
55 uint32_t FMT_CONTROL; \
/drivers/gpu/drm/radeon/
Dcikd.h984 #define FMT_CONTROL 0x6fb8 macro
Devergreend.h1373 #define FMT_CONTROL 0x6fb8 macro
Dr600d.h1242 #define FMT_CONTROL 0x6700 macro
/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_resource.h526 SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \