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Searched refs:GPCPLL_CFG2 (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgm20b.c167 val = nvkm_rd32(device, GPCPLL_CFG2); in gm20b_pllg_read_mnp()
177 nvkm_mask(device, GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_MASK, in gm20b_pllg_write_mnp()
290 nvkm_mask(device, GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_NEW_MASK, in gm20b_pllg_slide()
309 nvkm_mask(device, GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_MASK, in gm20b_pllg_slide()
Dgk20a.h41 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) macro
Dgk20a.c534 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, in gk20a_clk_setup_slide()