Searched refs:HHI_VID_CLK_DIV (Results 1 – 9 of 9) sorted by relevance
/drivers/gpu/drm/meson/ |
D | meson_vclk.c | 66 #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ macro 314 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_venci_cvbs_clock_config() 887 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() 950 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() 954 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() 964 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() 968 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() 978 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() 982 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() 992 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set() [all …]
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/drivers/clk/meson/ |
D | axg.h | 61 #define HHI_VID_CLK_DIV 0x164 macro
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D | gxbb.h | 44 #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ macro
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D | meson8b.h | 35 #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ macro
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D | g12a.h | 62 #define HHI_VID_CLK_DIV 0x164 macro
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D | meson8b.c | 1210 .offset = HHI_VID_CLK_DIV, 1252 .offset = HHI_VID_CLK_DIV, 1611 .offset = HHI_VID_CLK_DIV, 1642 .offset = HHI_VID_CLK_DIV, 1673 .offset = HHI_VID_CLK_DIV,
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D | gxbb.c | 1906 .offset = HHI_VID_CLK_DIV, 1934 .offset = HHI_VID_CLK_DIV, 2254 .offset = HHI_VID_CLK_DIV, 2270 .offset = HHI_VID_CLK_DIV,
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D | axg.c | 1329 .offset = HHI_VID_CLK_DIV, 1357 .offset = HHI_VID_CLK_DIV,
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D | g12a.c | 3172 .offset = HHI_VID_CLK_DIV, 3200 .offset = HHI_VID_CLK_DIV, 3520 .offset = HHI_VID_CLK_DIV, 3536 .offset = HHI_VID_CLK_DIV,
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