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Searched refs:HVS_WRITE (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/vc4/
Dvc4_hvs.c227 HVS_WRITE(SCALER_GAMADDR, in vc4_hvs_lut_load()
232 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); in vc4_hvs_lut_load()
234 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); in vc4_hvs_lut_load()
236 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); in vc4_hvs_lut_load()
361 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); in vc4_hvs_init_channel()
362 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); in vc4_hvs_init_channel()
363 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); in vc4_hvs_init_channel()
389 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl); in vc4_hvs_init_channel()
394 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx | in vc4_hvs_init_channel()
419 HVS_WRITE(SCALER_DISPCTRLX(chan), in vc4_hvs_stop_channel()
[all …]
Dvc4_kms.c166 HVS_WRITE(SCALER_OLEDCOEF2, in vc4_ctm_commit()
173 HVS_WRITE(SCALER_OLEDCOEF1, in vc4_ctm_commit()
180 HVS_WRITE(SCALER_OLEDCOEF0, in vc4_ctm_commit()
189 HVS_WRITE(SCALER_OLEDOFFS, in vc4_ctm_commit()
269 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux); in vc4_hvs_pv_muxing_commit()
299 HVS_WRITE(SCALER_DISPECTRL, in vc5_hvs_pv_muxing_commit()
311 HVS_WRITE(SCALER_DISPCTRL, in vc5_hvs_pv_muxing_commit()
323 HVS_WRITE(SCALER_DISPEOLN, in vc5_hvs_pv_muxing_commit()
336 HVS_WRITE(SCALER_DISPDITHER, in vc5_hvs_pv_muxing_commit()
Dvc4_drv.h579 #define HVS_WRITE(offset, val) writel(val, hvs->regs + offset) macro