1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_H_ 4 #define _ICP_QAT_FW_H_ 5 #include <linux/types.h> 6 #include "icp_qat_hw.h" 7 8 #define QAT_FIELD_SET(flags, val, bitpos, mask) \ 9 { (flags) = (((flags) & (~((mask) << (bitpos)))) | \ 10 (((val) & (mask)) << (bitpos))) ; } 11 12 #define QAT_FIELD_GET(flags, bitpos, mask) \ 13 (((flags) >> (bitpos)) & (mask)) 14 15 #define ICP_QAT_FW_REQ_DEFAULT_SZ 128 16 #define ICP_QAT_FW_RESP_DEFAULT_SZ 32 17 #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8 18 #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF 19 #define ICP_QAT_FW_NUM_LONGWORDS_1 1 20 #define ICP_QAT_FW_NUM_LONGWORDS_2 2 21 #define ICP_QAT_FW_NUM_LONGWORDS_3 3 22 #define ICP_QAT_FW_NUM_LONGWORDS_4 4 23 #define ICP_QAT_FW_NUM_LONGWORDS_5 5 24 #define ICP_QAT_FW_NUM_LONGWORDS_6 6 25 #define ICP_QAT_FW_NUM_LONGWORDS_7 7 26 #define ICP_QAT_FW_NUM_LONGWORDS_10 10 27 #define ICP_QAT_FW_NUM_LONGWORDS_13 13 28 #define ICP_QAT_FW_NULL_REQ_SERV_ID 1 29 30 enum icp_qat_fw_comn_resp_serv_id { 31 ICP_QAT_FW_COMN_RESP_SERV_NULL, 32 ICP_QAT_FW_COMN_RESP_SERV_CPM_FW, 33 ICP_QAT_FW_COMN_RESP_SERV_DELIMITER 34 }; 35 36 enum icp_qat_fw_comn_request_id { 37 ICP_QAT_FW_COMN_REQ_NULL = 0, 38 ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3, 39 ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4, 40 ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7, 41 ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9, 42 ICP_QAT_FW_COMN_REQ_DELIMITER 43 }; 44 45 struct icp_qat_fw_comn_req_hdr_cd_pars { 46 union { 47 struct { 48 __u64 content_desc_addr; 49 __u16 content_desc_resrvd1; 50 __u8 content_desc_params_sz; 51 __u8 content_desc_hdr_resrvd2; 52 __u32 content_desc_resrvd3; 53 } s; 54 struct { 55 __u32 serv_specif_fields[4]; 56 } s1; 57 } u; 58 }; 59 60 struct icp_qat_fw_comn_req_mid { 61 __u64 opaque_data; 62 __u64 src_data_addr; 63 __u64 dest_data_addr; 64 __u32 src_length; 65 __u32 dst_length; 66 }; 67 68 struct icp_qat_fw_comn_req_cd_ctrl { 69 __u32 content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5]; 70 }; 71 72 struct icp_qat_fw_comn_req_hdr { 73 __u8 resrvd1; 74 __u8 service_cmd_id; 75 __u8 service_type; 76 __u8 hdr_flags; 77 __u16 serv_specif_flags; 78 __u16 comn_req_flags; 79 }; 80 81 struct icp_qat_fw_comn_req_rqpars { 82 __u32 serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13]; 83 }; 84 85 struct icp_qat_fw_comn_req { 86 struct icp_qat_fw_comn_req_hdr comn_hdr; 87 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; 88 struct icp_qat_fw_comn_req_mid comn_mid; 89 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; 90 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; 91 }; 92 93 struct icp_qat_fw_comn_error { 94 __u8 xlat_err_code; 95 __u8 cmp_err_code; 96 }; 97 98 struct icp_qat_fw_comn_resp_hdr { 99 __u8 resrvd1; 100 __u8 service_id; 101 __u8 response_type; 102 __u8 hdr_flags; 103 struct icp_qat_fw_comn_error comn_error; 104 __u8 comn_status; 105 __u8 cmd_id; 106 }; 107 108 struct icp_qat_fw_comn_resp { 109 struct icp_qat_fw_comn_resp_hdr comn_hdr; 110 __u64 opaque_data; 111 __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; 112 }; 113 114 #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1 115 #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0 116 #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7 117 #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1 118 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F 119 120 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \ 121 icp_qat_fw_comn_req_hdr_t.service_type 122 123 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \ 124 icp_qat_fw_comn_req_hdr_t.service_type = val 125 126 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \ 127 icp_qat_fw_comn_req_hdr_t.service_cmd_id 128 129 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \ 130 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val 131 132 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \ 133 ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags) 134 135 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \ 136 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) 137 138 #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \ 139 QAT_FIELD_GET(hdr_flags, \ 140 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 141 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 142 143 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \ 144 (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK) 145 146 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ 147 QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ 148 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 149 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 150 151 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \ 152 (((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \ 153 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) 154 155 #define QAT_COMN_PTR_TYPE_BITPOS 0 156 #define QAT_COMN_PTR_TYPE_MASK 0x1 157 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1 158 #define QAT_COMN_CD_FLD_TYPE_MASK 0x1 159 #define QAT_COMN_PTR_TYPE_FLAT 0x0 160 #define QAT_COMN_PTR_TYPE_SGL 0x1 161 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0 162 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1 163 164 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \ 165 ((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \ 166 | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS)) 167 168 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \ 169 QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK) 170 171 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \ 172 QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \ 173 QAT_COMN_CD_FLD_TYPE_MASK) 174 175 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ 176 QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \ 177 QAT_COMN_PTR_TYPE_MASK) 178 179 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ 180 QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \ 181 QAT_COMN_CD_FLD_TYPE_MASK) 182 183 #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4 184 #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0 185 #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0 186 #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F 187 188 #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \ 189 ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \ 190 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 191 192 #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 193 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ 194 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 195 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ 196 & ICP_QAT_FW_COMN_NEXT_ID_MASK)); } 197 198 #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \ 199 (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) 200 201 #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 202 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ 203 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 204 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); } 205 206 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7 207 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1 208 #define QAT_COMN_RESP_PKE_STATUS_BITPOS 6 209 #define QAT_COMN_RESP_PKE_STATUS_MASK 0x1 210 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5 211 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1 212 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4 213 #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1 214 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3 215 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1 216 217 #define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \ 218 ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \ 219 QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \ 220 (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \ 221 QAT_COMN_RESP_CMP_STATUS_BITPOS) | \ 222 (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \ 223 QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \ 224 (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \ 225 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS)) 226 227 #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \ 228 QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \ 229 QAT_COMN_RESP_CRYPTO_STATUS_MASK) 230 231 #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \ 232 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \ 233 QAT_COMN_RESP_CMP_STATUS_MASK) 234 235 #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \ 236 QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \ 237 QAT_COMN_RESP_XLAT_STATUS_MASK) 238 239 #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \ 240 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \ 241 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) 242 243 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0 244 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1 245 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0 246 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1 247 #define ERR_CODE_NO_ERROR 0 248 #define ERR_CODE_INVALID_BLOCK_TYPE -1 249 #define ERR_CODE_NO_MATCH_ONES_COMP -2 250 #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3 251 #define ERR_CODE_INCOMPLETE_LEN -4 252 #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5 253 #define ERR_CODE_RPT_GT_SPEC_LEN -6 254 #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7 255 #define ERR_CODE_INV_DIS_CODE_LEN -8 256 #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9 257 #define ERR_CODE_DIS_TOO_FAR_BACK -10 258 #define ERR_CODE_OVERFLOW_ERROR -11 259 #define ERR_CODE_SOFT_ERROR -12 260 #define ERR_CODE_FATAL_ERROR -13 261 #define ERR_CODE_SSM_ERROR -14 262 #define ERR_CODE_ENDPOINT_ERROR -15 263 264 enum icp_qat_fw_slice { 265 ICP_QAT_FW_SLICE_NULL = 0, 266 ICP_QAT_FW_SLICE_CIPHER = 1, 267 ICP_QAT_FW_SLICE_AUTH = 2, 268 ICP_QAT_FW_SLICE_DRAM_RD = 3, 269 ICP_QAT_FW_SLICE_DRAM_WR = 4, 270 ICP_QAT_FW_SLICE_COMP = 5, 271 ICP_QAT_FW_SLICE_XLAT = 6, 272 ICP_QAT_FW_SLICE_DELIMITER 273 }; 274 #endif 275