1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_DEFINES_H_ 5 #define _IGC_DEFINES_H_ 6 7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 8 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 9 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 10 11 #define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ 12 #define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */ 13 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 14 15 /* Definitions for power management and wakeup registers */ 16 /* Wake Up Control */ 17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */ 18 19 /* Wake Up Filter Control */ 20 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 21 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 22 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 23 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 24 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 25 #define IGC_WUFC_FLEX_HQ BIT(14) /* Flex Filters Host Queuing */ 26 #define IGC_WUFC_FLX0 BIT(16) /* Flexible Filter 0 Enable */ 27 #define IGC_WUFC_FLX1 BIT(17) /* Flexible Filter 1 Enable */ 28 #define IGC_WUFC_FLX2 BIT(18) /* Flexible Filter 2 Enable */ 29 #define IGC_WUFC_FLX3 BIT(19) /* Flexible Filter 3 Enable */ 30 #define IGC_WUFC_FLX4 BIT(20) /* Flexible Filter 4 Enable */ 31 #define IGC_WUFC_FLX5 BIT(21) /* Flexible Filter 5 Enable */ 32 #define IGC_WUFC_FLX6 BIT(22) /* Flexible Filter 6 Enable */ 33 #define IGC_WUFC_FLX7 BIT(23) /* Flexible Filter 7 Enable */ 34 35 #define IGC_WUFC_FILTER_MASK GENMASK(23, 14) 36 37 #define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 38 39 /* Wake Up Status */ 40 #define IGC_WUS_EX 0x00000004 /* Directed Exact */ 41 #define IGC_WUS_ARPD 0x00000020 /* Directed ARP Request */ 42 #define IGC_WUS_IPV4 0x00000040 /* Directed IPv4 */ 43 #define IGC_WUS_IPV6 0x00000080 /* Directed IPv6 */ 44 #define IGC_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */ 45 46 /* Packet types that are enabled for wake packet delivery */ 47 #define WAKE_PKT_WUS ( \ 48 IGC_WUS_EX | \ 49 IGC_WUS_ARPD | \ 50 IGC_WUS_IPV4 | \ 51 IGC_WUS_IPV6 | \ 52 IGC_WUS_NSD) 53 54 /* Wake Up Packet Length */ 55 #define IGC_WUPL_MASK 0x00000FFF 56 57 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */ 58 #define IGC_WUPM_BYTES 128 59 60 /* Wakeup Filter Control Extended */ 61 #define IGC_WUFC_EXT_FLX8 BIT(8) /* Flexible Filter 8 Enable */ 62 #define IGC_WUFC_EXT_FLX9 BIT(9) /* Flexible Filter 9 Enable */ 63 #define IGC_WUFC_EXT_FLX10 BIT(10) /* Flexible Filter 10 Enable */ 64 #define IGC_WUFC_EXT_FLX11 BIT(11) /* Flexible Filter 11 Enable */ 65 #define IGC_WUFC_EXT_FLX12 BIT(12) /* Flexible Filter 12 Enable */ 66 #define IGC_WUFC_EXT_FLX13 BIT(13) /* Flexible Filter 13 Enable */ 67 #define IGC_WUFC_EXT_FLX14 BIT(14) /* Flexible Filter 14 Enable */ 68 #define IGC_WUFC_EXT_FLX15 BIT(15) /* Flexible Filter 15 Enable */ 69 #define IGC_WUFC_EXT_FLX16 BIT(16) /* Flexible Filter 16 Enable */ 70 #define IGC_WUFC_EXT_FLX17 BIT(17) /* Flexible Filter 17 Enable */ 71 #define IGC_WUFC_EXT_FLX18 BIT(18) /* Flexible Filter 18 Enable */ 72 #define IGC_WUFC_EXT_FLX19 BIT(19) /* Flexible Filter 19 Enable */ 73 #define IGC_WUFC_EXT_FLX20 BIT(20) /* Flexible Filter 20 Enable */ 74 #define IGC_WUFC_EXT_FLX21 BIT(21) /* Flexible Filter 21 Enable */ 75 #define IGC_WUFC_EXT_FLX22 BIT(22) /* Flexible Filter 22 Enable */ 76 #define IGC_WUFC_EXT_FLX23 BIT(23) /* Flexible Filter 23 Enable */ 77 #define IGC_WUFC_EXT_FLX24 BIT(24) /* Flexible Filter 24 Enable */ 78 #define IGC_WUFC_EXT_FLX25 BIT(25) /* Flexible Filter 25 Enable */ 79 #define IGC_WUFC_EXT_FLX26 BIT(26) /* Flexible Filter 26 Enable */ 80 #define IGC_WUFC_EXT_FLX27 BIT(27) /* Flexible Filter 27 Enable */ 81 #define IGC_WUFC_EXT_FLX28 BIT(28) /* Flexible Filter 28 Enable */ 82 #define IGC_WUFC_EXT_FLX29 BIT(29) /* Flexible Filter 29 Enable */ 83 #define IGC_WUFC_EXT_FLX30 BIT(30) /* Flexible Filter 30 Enable */ 84 #define IGC_WUFC_EXT_FLX31 BIT(31) /* Flexible Filter 31 Enable */ 85 86 #define IGC_WUFC_EXT_FILTER_MASK GENMASK(31, 8) 87 88 /* Loop limit on how long we wait for auto-negotiation to complete */ 89 #define COPPER_LINK_UP_LIMIT 10 90 #define PHY_AUTO_NEG_LIMIT 45 91 92 /* Number of 100 microseconds we wait for PCI Express master disable */ 93 #define MASTER_DISABLE_TIMEOUT 800 94 /*Blocks new Master requests */ 95 #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004 96 /* Status of Master requests. */ 97 #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000 98 99 /* Receive Address 100 * Number of high/low register pairs in the RAR. The RAR (Receive Address 101 * Registers) holds the directed and multicast addresses that we monitor. 102 * Technically, we have 16 spots. However, we reserve one of these spots 103 * (RAR[15]) for our directed address used by controllers with 104 * manageability enabled, allowing us room for 15 multicast addresses. 105 */ 106 #define IGC_RAH_RAH_MASK 0x0000FFFF 107 #define IGC_RAH_ASEL_MASK 0x00030000 108 #define IGC_RAH_ASEL_SRC_ADDR BIT(16) 109 #define IGC_RAH_QSEL_MASK 0x000C0000 110 #define IGC_RAH_QSEL_SHIFT 18 111 #define IGC_RAH_QSEL_ENABLE BIT(28) 112 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */ 113 114 #define IGC_RAL_MAC_ADDR_LEN 4 115 #define IGC_RAH_MAC_ADDR_LEN 2 116 117 /* Error Codes */ 118 #define IGC_SUCCESS 0 119 #define IGC_ERR_NVM 1 120 #define IGC_ERR_PHY 2 121 #define IGC_ERR_CONFIG 3 122 #define IGC_ERR_PARAM 4 123 #define IGC_ERR_MAC_INIT 5 124 #define IGC_ERR_RESET 9 125 #define IGC_ERR_MASTER_REQUESTS_PENDING 10 126 #define IGC_ERR_BLK_PHY_RESET 12 127 #define IGC_ERR_SWFW_SYNC 13 128 129 /* Device Control */ 130 #define IGC_CTRL_RST 0x04000000 /* Global reset */ 131 132 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 133 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 134 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */ 135 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 136 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 137 138 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 139 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 140 141 #define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ 142 #define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ 143 144 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */ 145 #define MAX_JUMBO_FRAME_SIZE 0x2600 146 147 /* PBA constants */ 148 #define IGC_PBA_34K 0x0022 149 150 /* SW Semaphore Register */ 151 #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 152 #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 153 154 /* SWFW_SYNC Definitions */ 155 #define IGC_SWFW_EEP_SM 0x1 156 #define IGC_SWFW_PHY0_SM 0x2 157 158 /* Autoneg Advertisement Register */ 159 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 160 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 161 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 162 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 163 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 164 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 165 166 /* Link Partner Ability Register (Base Page) */ 167 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 168 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 169 170 /* 1000BASE-T Control Register */ 171 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 172 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 173 174 /* 1000BASE-T Status Register */ 175 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 176 177 /* PHY GPY 211 registers */ 178 #define STANDARD_AN_REG_MASK 0x0007 /* MMD */ 179 #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ 180 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ 181 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ 182 183 /* NVM Control */ 184 /* Number of milliseconds for NVM auto read done after MAC reset. */ 185 #define AUTO_READ_DONE_TIMEOUT 10 186 #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 187 #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */ 188 #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */ 189 /* NVM Addressing bits based on type 0=small, 1=large */ 190 #define IGC_EECD_ADDR_BITS 0x00000400 191 #define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 192 #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 193 #define IGC_EECD_SIZE_EX_SHIFT 11 194 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */ 195 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/ 196 #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */ 197 #define IGC_FLUDONE_ATTEMPTS 20000 198 #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 199 200 /* Offset to data in NVM read/write registers */ 201 #define IGC_NVM_RW_REG_DATA 16 202 #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 203 #define IGC_NVM_RW_REG_START 1 /* Start operation */ 204 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 205 #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */ 206 #define IGC_NVM_DEV_STARTER 5 /* Dev_starter Version */ 207 208 /* NVM Word Offsets */ 209 #define NVM_CHECKSUM_REG 0x003F 210 211 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 212 #define NVM_SUM 0xBABA 213 #define NVM_WORD_SIZE_BASE_SHIFT 6 214 215 /* Collision related configuration parameters */ 216 #define IGC_COLLISION_THRESHOLD 15 217 #define IGC_CT_SHIFT 4 218 #define IGC_COLLISION_DISTANCE 63 219 #define IGC_COLD_SHIFT 12 220 221 /* Device Status */ 222 #define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 223 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 224 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 225 #define IGC_STATUS_FUNC_SHIFT 2 226 #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */ 227 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 228 #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 229 #define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */ 230 231 #define SPEED_10 10 232 #define SPEED_100 100 233 #define SPEED_1000 1000 234 #define SPEED_2500 2500 235 #define HALF_DUPLEX 1 236 #define FULL_DUPLEX 2 237 238 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */ 239 #define ADVERTISE_10_HALF 0x0001 240 #define ADVERTISE_10_FULL 0x0002 241 #define ADVERTISE_100_HALF 0x0004 242 #define ADVERTISE_100_FULL 0x0008 243 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 244 #define ADVERTISE_1000_FULL 0x0020 245 #define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */ 246 #define ADVERTISE_2500_FULL 0x0080 247 248 #define IGC_ALL_SPEED_DUPLEX_2500 ( \ 249 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 250 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 251 252 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500 253 254 /* Interrupt Cause Read */ 255 #define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */ 256 #define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */ 257 #define IGC_ICR_LSC BIT(2) /* Link Status Change */ 258 #define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */ 259 #define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */ 260 #define IGC_ICR_RXO BIT(6) /* Rx overrun */ 261 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */ 262 #define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */ 263 #define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */ 264 265 /* If this bit asserted, the driver should claim the interrupt */ 266 #define IGC_ICR_INT_ASSERTED BIT(31) 267 268 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 269 270 #define IMS_ENABLE_MASK ( \ 271 IGC_IMS_RXT0 | \ 272 IGC_IMS_TXDW | \ 273 IGC_IMS_RXDMT0 | \ 274 IGC_IMS_RXSEQ | \ 275 IGC_IMS_LSC) 276 277 /* Interrupt Mask Set */ 278 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */ 279 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 280 #define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */ 281 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */ 282 #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */ 283 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 284 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 285 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */ 286 287 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */ 288 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */ 289 290 /* Interrupt Cause Set */ 291 #define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */ 292 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */ 293 294 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 295 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 296 #define IGC_IVAR_VALID 0x80 297 #define IGC_GPIE_NSICR 0x00000001 298 #define IGC_GPIE_MSIX_MODE 0x00000010 299 #define IGC_GPIE_EIAME 0x40000000 300 #define IGC_GPIE_PBA 0x80000000 301 302 /* Receive Descriptor bit definitions */ 303 #define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */ 304 305 /* Transmit Descriptor bit definitions */ 306 #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 307 #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 308 #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 309 #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 310 #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */ 311 #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 312 #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 313 #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 314 #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 315 #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */ 316 #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */ 317 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 318 #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 319 320 /* IPSec Encrypt Enable */ 321 #define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 322 #define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 323 324 #define IGC_ADVTXD_TSN_CNTX_FIRST 0x00000080 325 326 /* Transmit Control */ 327 #define IGC_TCTL_EN 0x00000002 /* enable Tx */ 328 #define IGC_TCTL_PSP 0x00000008 /* pad short packets */ 329 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */ 330 #define IGC_TCTL_COLD 0x003ff000 /* collision distance */ 331 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 332 333 /* Flow Control Constants */ 334 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 335 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 336 #define FLOW_CONTROL_TYPE 0x8808 337 /* Enable XON frame transmission */ 338 #define IGC_FCRTL_XONE 0x80000000 339 340 /* Management Control */ 341 #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 342 #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 343 344 /* Receive Control */ 345 #define IGC_RCTL_RST 0x00000001 /* Software reset */ 346 #define IGC_RCTL_EN 0x00000002 /* enable */ 347 #define IGC_RCTL_SBP 0x00000004 /* store bad packet */ 348 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */ 349 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */ 350 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */ 351 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 352 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 353 354 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 355 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */ 356 357 /* Split Replication Receive Control */ 358 #define IGC_SRRCTL_TIMESTAMP 0x40000000 359 #define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14) 360 #define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17) 361 362 /* Receive Descriptor bit definitions */ 363 #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */ 364 #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 365 #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 366 #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 367 #define IGC_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 368 369 #define IGC_RXDEXT_STATERR_LB 0x00040000 370 371 /* Advanced Receive Descriptor bit definitions */ 372 #define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 373 374 #define IGC_RXDEXT_STATERR_L4E 0x20000000 375 #define IGC_RXDEXT_STATERR_IPE 0x40000000 376 #define IGC_RXDEXT_STATERR_RXE 0x80000000 377 378 #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 379 #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000 380 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 381 #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000 382 #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 383 384 /* Header split receive */ 385 #define IGC_RFCTL_IPV6_EX_DIS 0x00010000 386 #define IGC_RFCTL_LEF 0x00040000 387 388 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 389 390 #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */ 391 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */ 392 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */ 393 #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 394 #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 395 396 #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 397 #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 398 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 399 400 #define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */ 401 402 #define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */ 403 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */ 404 405 /* Time Sync Interrupt Causes */ 406 #define IGC_TSICR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */ 407 #define IGC_TSICR_TXTS BIT(1) /* Transmit Timestamp. */ 408 #define IGC_TSICR_TT0 BIT(3) /* Target Time 0 Trigger. */ 409 #define IGC_TSICR_TT1 BIT(4) /* Target Time 1 Trigger. */ 410 #define IGC_TSICR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */ 411 #define IGC_TSICR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */ 412 413 #define IGC_TSICR_INTERRUPTS IGC_TSICR_TXTS 414 415 #define IGC_FTQF_VF_BP 0x00008000 416 #define IGC_FTQF_1588_TIME_STAMP 0x08000000 417 #define IGC_FTQF_MASK 0xF0000000 418 #define IGC_FTQF_MASK_PROTO_BP 0x10000000 419 420 /* Time Sync Receive Control bit definitions */ 421 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 422 #define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00 423 #define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02 424 #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 425 #define IGC_TSYNCRXCTL_TYPE_ALL 0x08 426 #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 427 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 428 #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 429 #define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 /* Sample RX tstamp in PHY sop */ 430 431 /* Time Sync Receive Configuration */ 432 #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 433 #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 434 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 435 436 /* Immediate Interrupt Receive */ 437 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 438 #define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 439 #define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 440 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 441 442 /* Immediate Interrupt Receive Extended */ 443 #define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 444 #define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 445 446 /* Time Sync Transmit Control bit definitions */ 447 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */ 448 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 449 #define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 450 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ 451 #define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 452 #define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 453 #define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */ 454 455 /* Timer selection bits */ 456 #define IGC_AUX_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for auxiliary time stamp */ 457 #define IGC_AUX_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for auxiliary time stamp */ 458 #define IGC_AUX_IO_TIMER_SEL_SYSTIM2 (2u << 30) /* Select SYSTIM2 for auxiliary time stamp */ 459 #define IGC_AUX_IO_TIMER_SEL_SYSTIM3 (3u << 30) /* Select SYSTIM3 for auxiliary time stamp */ 460 #define IGC_TT_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for target time stamp */ 461 #define IGC_TT_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for target time stamp */ 462 #define IGC_TT_IO_TIMER_SEL_SYSTIM2 (2u << 30) /* Select SYSTIM2 for target time stamp */ 463 #define IGC_TT_IO_TIMER_SEL_SYSTIM3 (3u << 30) /* Select SYSTIM3 for target time stamp */ 464 465 /* TSAUXC Configuration Bits */ 466 #define IGC_TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */ 467 #define IGC_TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */ 468 #define IGC_TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */ 469 #define IGC_TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */ 470 #define IGC_TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */ 471 #define IGC_TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */ 472 #define IGC_TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */ 473 #define IGC_TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */ 474 #define IGC_TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */ 475 #define IGC_TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */ 476 #define IGC_TSAUXC_PLSG BIT(17) /* Generate a pulse. */ 477 #define IGC_TSAUXC_DISABLE1 BIT(27) /* Disable SYSTIM0 Count Operation. */ 478 #define IGC_TSAUXC_DISABLE2 BIT(28) /* Disable SYSTIM1 Count Operation. */ 479 #define IGC_TSAUXC_DISABLE3 BIT(29) /* Disable SYSTIM2 Count Operation. */ 480 #define IGC_TSAUXC_DIS_TS_CLEAR BIT(30) /* Disable EN_TT0/1 auto clear. */ 481 #define IGC_TSAUXC_DISABLE0 BIT(31) /* Disable SYSTIM0 Count Operation. */ 482 483 /* SDP Configuration Bits */ 484 #define IGC_AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 485 #define IGC_AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 486 #define IGC_AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 487 #define IGC_AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 488 #define IGC_AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */ 489 #define IGC_AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 490 #define IGC_AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 491 #define IGC_AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 492 #define IGC_AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 493 #define IGC_AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */ 494 #define IGC_TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */ 495 #define IGC_TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */ 496 #define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */ 497 #define IGC_TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */ 498 #define IGC_TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */ 499 #define IGC_TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */ 500 #define IGC_TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */ 501 #define IGC_TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */ 502 #define IGC_TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */ 503 #define IGC_TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */ 504 #define IGC_TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */ 505 #define IGC_TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */ 506 #define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */ 507 #define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */ 508 #define IGC_TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */ 509 #define IGC_TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */ 510 #define IGC_TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */ 511 #define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */ 512 #define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */ 513 #define IGC_TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */ 514 515 /* Transmit Scheduling */ 516 #define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001 517 #define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008 518 #define IGC_TQAVCTRL_FUTSCDDIS 0x00000080 519 520 #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001 521 #define IGC_TXQCTL_STRICT_CYCLE 0x00000002 522 #define IGC_TXQCTL_STRICT_END 0x00000004 523 #define IGC_TXQCTL_QAV_SEL_MASK 0x000000C0 524 #define IGC_TXQCTL_QAV_SEL_CBS0 0x00000080 525 #define IGC_TXQCTL_QAV_SEL_CBS1 0x000000C0 526 527 #define IGC_TQAVCC_IDLESLOPE_MASK 0xFFFF 528 #define IGC_TQAVCC_KEEP_CREDITS BIT(30) 529 530 #define IGC_MAX_SR_QUEUES 2 531 532 /* Receive Checksum Control */ 533 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 534 #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 535 536 /* PCIe PTM Control */ 537 #define IGC_PTM_CTRL_START_NOW BIT(29) /* Start PTM Now */ 538 #define IGC_PTM_CTRL_EN BIT(30) /* Enable PTM */ 539 #define IGC_PTM_CTRL_TRIG BIT(31) /* PTM Cycle trigger */ 540 #define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2) 541 #define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8) 542 543 #define IGC_PTM_SHORT_CYC_DEFAULT 10 /* Default Short/interrupted cycle interval */ 544 #define IGC_PTM_CYC_TIME_DEFAULT 5 /* Default PTM cycle time */ 545 #define IGC_PTM_TIMEOUT_DEFAULT 255 /* Default timeout for PTM errors */ 546 547 /* PCIe Digital Delay */ 548 #define IGC_PCIE_DIG_DELAY_DEFAULT 0x01440000 549 550 /* PCIe PHY Delay */ 551 #define IGC_PCIE_PHY_DELAY_DEFAULT 0x40900000 552 553 #define IGC_TIMADJ_ADJUST_METH 0x40000000 554 555 /* PCIe PTM Status */ 556 #define IGC_PTM_STAT_VALID BIT(0) /* PTM Status */ 557 #define IGC_PTM_STAT_RET_ERR BIT(1) /* Root port timeout */ 558 #define IGC_PTM_STAT_BAD_PTM_RES BIT(2) /* PTM Response msg instead of PTM Response Data */ 559 #define IGC_PTM_STAT_T4M1_OVFL BIT(3) /* T4 minus T1 overflow */ 560 #define IGC_PTM_STAT_ADJUST_1ST BIT(4) /* 1588 timer adjusted during 1st PTM cycle */ 561 #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */ 562 563 /* PCIe PTM Cycle Control */ 564 #define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec) ((msec) & 0x3ff) /* PTM Cycle Time (msec) */ 565 #define IGC_PTM_CYCLE_CTRL_AUTO_CYC_EN BIT(31) /* PTM Cycle Control */ 566 567 /* GPY211 - I225 defines */ 568 #define GPY_MMD_MASK 0xFFFF0000 569 #define GPY_MMD_SHIFT 16 570 #define GPY_REG_MASK 0x0000FFFF 571 572 #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 573 574 /* MAC definitions */ 575 #define IGC_FACTPS_MNGCG 0x20000000 576 #define IGC_FWSM_MODE_MASK 0xE 577 #define IGC_FWSM_MODE_SHIFT 1 578 579 /* Management Control */ 580 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 581 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 582 583 /* PHY */ 584 #define PHY_REVISION_MASK 0xFFFFFFF0 585 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 586 #define IGC_GEN_POLL_TIMEOUT 1920 587 588 /* PHY Control Register */ 589 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 590 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 591 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 592 593 /* PHY Status Register */ 594 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 595 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 596 #define IGC_PHY_RST_COMP 0x0100 /* Internal PHY reset completion */ 597 598 /* PHY 1000 MII Register/Bit Definitions */ 599 /* PHY Registers defined by IEEE */ 600 #define PHY_CONTROL 0x00 /* Control Register */ 601 #define PHY_STATUS 0x01 /* Status Register */ 602 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 603 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 604 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 605 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 606 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 607 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 608 609 /* MDI Control */ 610 #define IGC_MDIC_DATA_MASK 0x0000FFFF 611 #define IGC_MDIC_REG_MASK 0x001F0000 612 #define IGC_MDIC_REG_SHIFT 16 613 #define IGC_MDIC_PHY_MASK 0x03E00000 614 #define IGC_MDIC_PHY_SHIFT 21 615 #define IGC_MDIC_OP_WRITE 0x04000000 616 #define IGC_MDIC_OP_READ 0x08000000 617 #define IGC_MDIC_READY 0x10000000 618 #define IGC_MDIC_ERROR 0x40000000 619 620 #define IGC_N0_QUEUE -1 621 622 #define IGC_MAX_MAC_HDR_LEN 127 623 #define IGC_MAX_NETWORK_HDR_LEN 511 624 625 #define IGC_VLANPQF_QSEL(_n, q_idx) ((q_idx) << ((_n) * 4)) 626 #define IGC_VLANPQF_VALID(_n) (0x1 << (3 + (_n) * 4)) 627 #define IGC_VLANPQF_QUEUE_MASK 0x03 628 629 #define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 630 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */ 631 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet Type of TCP */ 632 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */ 633 634 /* Maximum size of the MTA register table in all supported adapters */ 635 #define MAX_MTA_REG 128 636 637 /* EEE defines */ 638 #define IGC_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */ 639 #define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 640 #define IGC_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 641 #define IGC_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 642 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 643 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 644 #define IGC_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 645 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 646 647 /* LTR defines */ 648 #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */ 649 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */ 650 #define IGC_TW_SYSTEM_1000_MASK 0x000000FF 651 /* Minimum time for 100BASE-T where no data will be transmit following move out 652 * of EEE LPI Tx state 653 */ 654 #define IGC_TW_SYSTEM_100_MASK 0x0000FF00 655 #define IGC_TW_SYSTEM_100_SHIFT 8 656 #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 657 #define IGC_DMACR_DMACTHR_MASK 0x00FF0000 658 #define IGC_DMACR_DMACTHR_SHIFT 16 659 /* Reg val to set scale to 1024 nsec */ 660 #define IGC_LTRMINV_SCALE_1024 2 661 /* Reg val to set scale to 32768 nsec */ 662 #define IGC_LTRMINV_SCALE_32768 3 663 /* Reg val to set scale to 1024 nsec */ 664 #define IGC_LTRMAXV_SCALE_1024 2 665 /* Reg val to set scale to 32768 nsec */ 666 #define IGC_LTRMAXV_SCALE_32768 3 667 #define IGC_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */ 668 #define IGC_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */ 669 #define IGC_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ 670 #define IGC_LTRMINV_SCALE_SHIFT 10 671 #define IGC_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ 672 #define IGC_LTRMAXV_SCALE_SHIFT 10 673 674 #endif /* _IGC_DEFINES_H_ */ 675