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Searched refs:IS_DG2 (Results 1 – 25 of 30) sorted by relevance

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/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c786 else if (IS_DG2(i915)) in __intel_engine_init_ctx_wa()
1536 else if (IS_DG2(i915)) in gt_init_workarounds()
2001 else if (IS_DG2(i915)) in intel_engine_init_whitelist()
2109 if (IS_DG2(i915)) { in rcs_engine_wa_init()
2275 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()
2685 if (IS_DG2(i915)) { in add_render_compute_tuning_settings()
2767 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { in general_render_compute_wa_init()
Dintel_gsc.c177 } else if (IS_DG2(i915)) { in gsc_init_one()
Dintel_gt_mcr.c114 } else if (IS_DG2(i915)) { in intel_gt_mcr_init()
Dintel_mocs.c454 } else if (IS_DG2(i915)) { in get_mocs_settings()
Dintel_reset.c653 if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES) in gen8_reset_engines()
Dintel_lrc.c1302 if (IS_DG2(ce->engine->i915)) in gen12_emit_indirect_ctx_rcs()
/drivers/gpu/drm/i915/display/
Dintel_dmc.c330 if (IS_DG2(i915)) { in get_flip_queue_event_regs()
348 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) in disable_all_flip_queue_events()
904 if (IS_DG2(dev_priv)) { in intel_dmc_ucode_init()
Dintel_cdclk.c1225 return IS_DG2(i915); in has_cdclk_squasher()
1452 if (IS_DG2(dev_priv)) in bxt_de_pll_readout()
2311 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()
3208 if (IS_DG2(dev_priv)) { in intel_init_cdclk_hooks()
Dintel_display_power.c911 if (IS_DG2(dev_priv)) in get_allowed_dc_mask()
1657 if (IS_DG2(dev_priv)) in icl_display_core_init()
Dintel_bw.c631 else if (IS_DG2(dev_priv)) in intel_bw_init_hw()
Dintel_ddi_buf_trans.c1614 if (IS_DG2(i915)) { in intel_ddi_buf_trans_init()
Dintel_ddi.c194 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); in intel_wait_ddi_buf_active()
4358 if (IS_DG2(dev_priv)) { in intel_ddi_init()
4416 if (IS_DG2(dev_priv)) { in intel_ddi_init()
Dintel_fbc.c818 if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915)) in intel_fbc_program_workarounds()
Dintel_display_power_well.c260 if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) { in hsw_wait_for_power_well_enable()
Dskl_watermark.c1309 if (IS_DG2(i915)) in skl_compute_dbuf_slices()
3244 int mult = IS_DG2(i915) ? 2 : 1; in skl_read_wm_latency()
Dintel_snps_phy.c2004 if (!IS_DG2(i915)) in intel_mpllb_state_verify()
Dintel_display.c1020 if (IS_DG2(dev_priv)) in icl_set_pipe_chicken()
2109 if (IS_DG2(dev_priv)) in intel_phy_is_tc()
2126 else if (IS_DG2(dev_priv)) in intel_phy_is_snps()
7921 if (IS_DG2(dev_priv)) { in intel_setup_outputs()
Dintel_dpll.c1518 if (IS_DG2(dev_priv)) in intel_dpll_init_clock_hook()
Dintel_psr.c897 IS_DG2(dev_priv)) { in intel_psr2_config_valid()
Dintel_hdmi.c1878 if (IS_DG2(dev_priv)) in hdmi_port_clock_valid()
/drivers/gpu/drm/i915/
Di915_drv.h617 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) macro
765 (IS_DG2(__i915) && \
869 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
Dintel_pch.c223 } else if (IS_DG2(dev_priv)) { in intel_detect_pch()
Dintel_dram.c510 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) in intel_dram_detect()
/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.c269 if (IS_DG2(gt->i915)) in guc_ctl_wa_flags()
279 if (IS_DG2(gt->i915)) in guc_ctl_wa_flags()
Dintel_guc_capture.c411 if (IS_DG2(i915)) in guc_capture_get_device_reglist()

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