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Searched refs:ITR_REG_ALIGN (Results 1 – 8 of 8) sorted by relevance

/drivers/net/ethernet/intel/ice/
Dice_txrx.h235 #define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK) macro
Dice_lib.c2074 ITR_REG_ALIGN(itr) >> ICE_ITR_GRAN_S); in __ice_write_itr()
Dice_ethtool.c3884 ITR_REG_ALIGN(coalesce_usecs)); in ice_print_if_odd_usecs()
Dice_main.c3326 ITR_REG_ALIGN(ICE_ITR_8K) >> ICE_ITR_GRAN_S); in ice_req_irq_msix_misc()
/drivers/net/ethernet/intel/iavf/
Diavf_txrx.h25 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~IAVF_ITR_MASK) macro
Diavf_ethtool.c794 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs); in iavf_set_itr_per_queue()
795 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs); in iavf_set_itr_per_queue()
/drivers/net/ethernet/intel/i40e/
Di40e_txrx.h25 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK) macro
Di40e_ethtool.c2971 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs); in i40e_set_itr_per_queue()
2972 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs); in i40e_set_itr_per_queue()