Home
last modified time | relevance | path

Searched refs:KHZ (Results 1 – 11 of 11) sorted by relevance

/drivers/phy/samsung/
Dphy-samsung-usb2.h19 #define KHZ 1000 macro
20 #define MHZ (KHZ * KHZ)
Dphy-exynos5-usbdrd.c149 #define KHZ 1000 macro
150 #define MHZ (KHZ * KHZ)
230 case 9600 * KHZ: in exynos5_rate_to_clk()
239 case 19200 * KHZ: in exynos5_rate_to_clk()
Dphy-exynos4x12-usb2.c137 case 9600 * KHZ: in exynos4x12_rate_to_clk()
146 case 19200 * KHZ: in exynos4x12_rate_to_clk()
Dphy-exynos5250-usb2.c146 case 9600 * KHZ: in exynos5250_rate_to_clk()
155 case 19200 * KHZ: in exynos5250_rate_to_clk()
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk20a.h27 #define KHZ (1000) macro
28 #define MHZ (KHZ * 1000)
146 clk->parent_rate / KHZ); in gk20a_pllg_n_lo()
Dgk20a.c113 target_clk_f = rate * 2 / KHZ; in gk20a_pllg_calc_mnp()
114 ref_clk_f = clk->parent_rate / KHZ; in gk20a_pllg_calc_mnp()
195 target_clk_f / KHZ); in gk20a_pllg_calc_mnp()
205 target_freq / KHZ, pll->m, pll->n, pll->pl, in gk20a_pllg_calc_mnp()
530 clk->parent_rate / KHZ); in gk20a_clk_setup_slide()
635 clk->parent_rate / KHZ); in gk20a_clk_ctor()
Dgm20b.c490 u32 rate = gk20a_pllg_calc_rate(&clk->base, pll) / KHZ; in gm20b_dvfs_calc_safe_pll()
491 u32 parent_rate = clk->base.parent_rate / KHZ; in gm20b_dvfs_calc_safe_pll()
1046 (clk->base.parent_rate / KHZ)); in gm20b_clk_new()
/drivers/devfreq/
Dtegra30-devfreq.c68 #define KHZ 1000 macro
70 #define KHZ_MAX (ULONG_MAX / KHZ)
254 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
412 tegra->cur_freq = data->new_rate / KHZ; in tegra_actmon_clk_notify_cb()
567 tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; in tegra_actmon_resume()
668 stat->current_frequency = cur_freq * KHZ; in tegra_devfreq_get_dev_status()
724 *freq = target_freq * KHZ; in tegra_governor_get_target()
915 tegra->max_freq = rate / KHZ; in tegra_devfreq_probe()
/drivers/cpufreq/
Dtegra194-cpufreq.c21 #define KHZ 1000 macro
24 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
204 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
303 return (rate_mhz * KHZ); /* in KHz */ in tegra194_calculate_speed()
/drivers/i2c/busses/
Di2c-qcom-geni.c73 #define KHZ(freq) (1000 * freq) macro
142 {KHZ(100), 7, 10, 11, 26},
143 {KHZ(400), 2, 5, 12, 24},
144 {KHZ(1000), 1, 3, 9, 18},
786 gi2c->clk_freq_out = KHZ(100); in geni_i2c_probe()
/drivers/tty/serial/8250/
D8250_bcm7271.c190 #define KHZ 1000 macro
191 #define MHZ(x) ((x) * KHZ * KHZ)