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Searched refs:LANE_COUNT_FOUR (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_dio_stream_encoder.c79 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc32_stream_encoder_dvi_set_stream_attribute()
119 cntl.lanes_number = LANE_COUNT_FOUR; in enc32_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/virtual/
Dvirtual_link_encoder.c90 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, in virtual_link_encoder_get_max_link_cap()
/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_dio_stream_encoder.c112 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc314_stream_encoder_dvi_set_stream_attribute()
152 cntl.lanes_number = LANE_COUNT_FOUR; in enc314_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c547 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_stream_encoder_hdmi_set_stream_attribute()
664 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in dce110_stream_encoder_dvi_set_stream_attribute()
688 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_stream_encoder_lvds_set_stream_attribute()
Ddce_link_encoder.c971 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_link_encoder_hw_init()
1669 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, in dce110_link_encoder_get_max_link_cap()
/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h35 LANE_COUNT_FOUR = 4, enumerator
37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.c507 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc3_stream_encoder_dvi_set_stream_attribute()
553 cntl.lanes_number = LANE_COUNT_FOUR; in enc3_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/bios/
Dcommand_table.c232 if (LANE_COUNT_FOUR < cntl->lanes_number) in encoder_control_digx_v3()
278 if (LANE_COUNT_FOUR < cntl->lanes_number) in encoder_control_digx_v4()
477 if (LANE_COUNT_FOUR < cntl->lanes_number) { in transmitter_control_v2()
615 if (LANE_COUNT_FOUR < cntl->lanes_number) { in transmitter_control_v3()
749 if (LANE_COUNT_FOUR < cntl->lanes_number) in transmitter_control_v4()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c86 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
87 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
89 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
91 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
94 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
99 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
101 {LANE_COUNT_FOUR, LINK_RATE_LOW},
1150 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0) in dp_get_cr_failure()
1152 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0) in dp_get_cr_failure()
3392 case LANE_COUNT_FOUR: in reduce_lane_count()
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c840 cntl.lanes_number = LANE_COUNT_FOUR; in dcn10_link_encoder_hw_init()
1451 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, in dcn10_link_encoder_get_max_link_cap()
Ddcn10_stream_encoder.c495 cntl.lanes_number = LANE_COUNT_FOUR; in enc1_stream_encoder_hdmi_set_stream_attribute()
615 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; in enc1_stream_encoder_dvi_set_stream_attribute()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c288 case LANE_COUNT_FOUR: in dp_link_settings_write()
2975 case LANE_COUNT_FOUR: in edp_ilr_write()
Damdgpu_dm.c6400 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; in handle_edid_mgmt()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c882 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_edp_power_control()
1003 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_edp_backlight_control()