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Searched refs:MAX_DIVR_DIVISOR (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/analogbits/
Dwrpll-cln28hpc.c56 #define MAX_DIVR_DIVISOR 64 macro
197 c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent); in __wrpll_update_parent_rate()