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Searched refs:MAX_PHASE (Results 1 – 6 of 6) sorted by relevance

/drivers/mmc/host/
Drtsx_usb_sdmmc.c608 idx &= MAX_PHASE; in get_phase_point()
616 for (i = 0; i < MAX_PHASE + 1; i++) { in get_phase_len()
620 return MAX_PHASE + 1; in get_phase_len()
634 while (start < MAX_PHASE + 1) { in sd_search_final_phase()
643 final_phase = (start_final + len_final / 2) & MAX_PHASE; in sd_search_final_phase()
692 for (i = MAX_PHASE; i >= 0; i--) { in sd_tuning_phase()
/drivers/usb/host/
Duhci-q.c614 for (phase += period; phase < MAX_PHASE; phase += period) in uhci_highest_load()
633 int max_phase = min_t(int, MAX_PHASE, qh->period); in uhci_check_bandwidth()
665 for (i = qh->phase; i < MAX_PHASE; i += qh->period) { in uhci_reserve_bandwidth()
670 uhci->total_load / MAX_PHASE; in uhci_reserve_bandwidth()
698 for (i = qh->phase; i < MAX_PHASE; i += qh->period) { in uhci_release_bandwidth()
703 uhci->total_load / MAX_PHASE; in uhci_release_bandwidth()
1102 qh->phase = (qh->period / 2) & (MAX_PHASE - 1); in uhci_submit_interrupt()
Duhci-hcd.h95 #define MAX_PHASE 32 /* Periodic scheduling length */ macro
445 short load[MAX_PHASE]; /* Periodic allocations */
Duhci-debug.c399 for (i = 0; i < MAX_PHASE; ++i) { in uhci_sprint_schedule()
/drivers/staging/rts5208/
Dsd.h215 #define MAX_PHASE 31 macro
Dsd.c1616 struct timing_phase_path path[MAX_PHASE + 1];
1634 for (i = 0; i < MAX_PHASE + 1; i++) {
1668 path[cont_path_cnt - 1].end == MAX_PHASE) {
1669 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1673 path[0].mid += MAX_PHASE + 1;
1706 MAX_PHASE + 1);
1719 MAX_PHASE + 1);
1755 for (j = MAX_PHASE; j >= 0; j--) {
1799 for (i = MAX_PHASE; i >= 0; i--) {
1865 for (j = MAX_PHASE; j >= 0; j--) {