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Searched refs:MEID (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvid.h71 #define MEID(x) ((x) << 2) macro
Dcikd.h58 #define MEID(x) ((x) << 2) macro
Damdgpu_amdkfd_gfx_v7.c51 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
Damdgpu_amdkfd_gfx_v8.c45 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
Dsoc21.c214 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); in soc21_grbm_select()
Dnv.c317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); in nv_grbm_select()
Dsoc15.c360 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); in soc15_grbm_select()
Dvi.c584 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); in vi_srbm_select()
Dgfx_v11_0.c4518 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); in gfx_v11_0_soft_reset()
4532 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); in gfx_v11_0_soft_reset()
/drivers/gpu/drm/radeon/
Dcikd.h446 #define MEID(x) ((x) << 2) macro
Dcik.c1845 MEID(me & 0x3) | in cik_srbm_select()