Searched refs:MESON_SDHC_CLKC_CLK_DIV (Results 1 – 2 of 2) sorted by relevance
45 #define MESON_SDHC_CLKC_CLK_DIV GENMASK(11, 0) macro
297 rx_clk_phase = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val) / 4; in meson_mx_sdhc_set_clk()441 div = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val); in meson_mx_sdhc_execute_tuning()743 regmap_write(host->regmap, MESON_SDHC_CLKC, MESON_SDHC_CLKC_CLK_DIV); in meson_mx_sdhc_init_hw()