Searched refs:MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32 (Results 1 – 2 of 2) sorted by relevance
527 #define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32 \ macro
962 val |= MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32; in qed_int_deassertion_aeu_bit()