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Searched refs:NUM_BANKS (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c87 #define NUM_BANKS(x) ((x) << 20) macro
426 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
434 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
442 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
449 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init()
461 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
469 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
477 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
489 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
497 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
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Dgfx_v8_0.c76 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) macro
2224 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2228 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2232 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2236 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2240 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2244 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2248 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2252 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init()
2256 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init()
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Dgfx_v7_0.c1161 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
1165 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
1169 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
1173 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
1177 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
1181 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init()
1185 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init()
1189 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
1193 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
1197 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v7_0_tiling_mode_table_init()
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Dcikd.h197 # define NUM_BANKS(x) ((x) << 6) macro
Dsid.h1218 # define NUM_BANKS(x) ((x) << 20) macro
Ddce_v8_0.c1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
Ddce_v6_0.c1943 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
Ddce_v10_0.c1995 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
Dgfx_v9_0.c2046 NUM_BANKS); in gfx_v9_0_gpu_early_init()
/drivers/gpu/drm/radeon/
Dsi.c2519 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2528 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2537 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2546 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2555 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2564 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2573 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2582 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2591 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2600 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
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Dcik.c2439 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()
2443 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()
2447 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()
2451 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()
2455 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2459 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
2463 NUM_BANKS(ADDR_SURF_2_BANK)); in cik_tiling_mode_table_init()
2467 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()
2471 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()
2475 NUM_BANKS(ADDR_SURF_16_BANK)); in cik_tiling_mode_table_init()
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Dsid.h1221 # define NUM_BANKS(x) ((x) << 20) macro
Dcikd.h1275 # define NUM_BANKS(x) ((x) << 6) macro
/drivers/pinctrl/nomadik/
Dpinctrl-nomadik.c283 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) macro
544 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_glitch_slpm_init()
562 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_glitch_slpm_restore()
1528 static unsigned int slpm[NUM_BANKS]; in nmk_pmx_set()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.h269 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
467 type NUM_BANKS;\
Ddcn10_hubp.c150 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_plane.c177 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in fill_gfx8_tiling_info_from_flags()
/drivers/gpu/drm/amd/include/
Dnavi10_enum.h1549 typedef enum NUM_BANKS { enum
1555 } NUM_BANKS; typedef