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Searched refs:NUM_VCN_DPM_LEVELS (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu13_driver_if_v13_0_5.h47 #define NUM_VCN_DPM_LEVELS 4 macro
116 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
117 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
Dsmu13_driver_if_yellow_carp.h107 #define NUM_VCN_DPM_LEVELS 8 macro
126 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
127 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
Dsmu12_driver_if.h109 #define NUM_VCN_DPM_LEVELS 8 macro
121 DpmClock_t VClocks[NUM_VCN_DPM_LEVELS];
122 DpmClock_t DClocks[NUM_VCN_DPM_LEVELS];
Dsmu13_driver_if_v13_0_4.h108 #define NUM_VCN_DPM_LEVELS 8 macro
127 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
128 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
Dsmu11_driver_if_vangogh.h109 #define NUM_VCN_DPM_LEVELS 5 macro
134 vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS];
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_smu.h36 #define NUM_VCN_DPM_LEVELS 4 macro
74 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
75 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_smu.h36 #define NUM_VCN_DPM_LEVELS 8 macro
82 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
83 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_smu.h109 #define NUM_VCN_DPM_LEVELS 8 macro
135 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
136 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_smu.h54 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
55 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c233 if (dpm_level >= NUM_VCN_DPM_LEVELS) in renoir_get_dpm_clk_limited()
238 if (dpm_level >= NUM_VCN_DPM_LEVELS) in renoir_get_dpm_clk_limited()
576 count = NUM_VCN_DPM_LEVELS; in renoir_print_clk_levels()
580 count = NUM_VCN_DPM_LEVELS; in renoir_print_clk_levels()
784 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { in renoir_get_dpm_clock_table()
789 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { in renoir_get_dpm_clock_table()