Home
last modified time | relevance | path

Searched refs:NVWriteVgaCrtc (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv04/
Dhw.h119 static inline void NVWriteVgaCrtc(struct drm_device *dev, in NVWriteVgaCrtc() function
154 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); in NVWriteVgaCrtc5758()
155 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value); in NVWriteVgaCrtc5758()
160 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); in NVReadVgaCrtc5758()
281 NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11); in nv_lock_vga_crtc_base()
305 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21); in nv_lock_vga_crtc_shadow()
317 NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX, in NVLockVgaCrtcs()
321 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX, in NVLockVgaCrtcs()
366 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX, in nv_set_crtc_base()
382 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1); in nv_show_cursor()
Ddac.c155 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80); in nv04_dac_detect()
167 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, in nv04_dac_detect()
170 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0); in nv04_dac_detect()
222 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); in nv04_dac_detect()
223 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1); in nv04_dac_detect()
225 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode); in nv04_dac_detect()
Dtvnv04.c97 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A); in nv04_tv_dpms()
116 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX, in nv04_tv_bind()
118 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49, in nv04_tv_bind()
Dcursor.c33 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, in crtc_wr_cio_state()
Dhw.c101 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); in NVSetOwner()
104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); in NVSetOwner()
105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); in NVSetOwner()
390 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
Dcrtc.c59 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, in crtc_wr_cio_state()
230 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); in nv_crtc_dpms()
233 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); in nv_crtc_dpms()
739 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); in nv_crtc_commit()
Ddfp.c271 NVWriteVgaCrtc(dev, head ^ 1, in nv04_dfp_prepare()
/drivers/gpu/drm/nouveau/
Dnouveau_bios.c100 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB : in run_digital_op_script()