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Searched refs:PB_DIV_READY (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/microchip/
Dclk-core.c42 #define PB_DIV_READY BIT(11) macro
174 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
196 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()