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Searched refs:PERIP1_CLK_ENB (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/spear/
Dspear6xx_clock.c47 #define PERIP1_CLK_ENB (misc_base + 0x02C) macro
126 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); in spear6xx_clk_init()
172 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, in spear6xx_clk_init()
176 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, in spear6xx_clk_init()
193 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); in spear6xx_clk_init()
209 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); in spear6xx_clk_init()
228 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); in spear6xx_clk_init()
241 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); in spear6xx_clk_init()
254 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); in spear6xx_clk_init()
259 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); in spear6xx_clk_init()
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Dspear3xx_clock.c50 #define PERIP1_CLK_ENB (misc_base + 0x02C) macro
400 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); in spear3xx_clk_init()
448 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0, in spear3xx_clk_init()
466 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, in spear3xx_clk_init()
487 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, in spear3xx_clk_init()
499 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, in spear3xx_clk_init()
535 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, in spear3xx_clk_init()
549 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, in spear3xx_clk_init()
572 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, in spear3xx_clk_init()
576 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, in spear3xx_clk_init()
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