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Searched refs:PLL_CTL0_SEL (Results 1 – 1 of 1) sorted by relevance

/drivers/net/mdio/
Dmdio-mux-meson-g12a.c23 #define PLL_CTL0_SEL BIT(23) macro
268 mux->shift = __ffs(PLL_CTL0_SEL); in g12a_ephy_glue_clk_register()
269 mux->mask = PLL_CTL0_SEL >> mux->shift; in g12a_ephy_glue_clk_register()