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Searched refs:PORT_CLK_SEL (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Ddisplay.c414 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= in emulate_monitor_status_change()
416 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= in emulate_monitor_status_change()
440 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= in emulate_monitor_status_change()
442 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= in emulate_monitor_status_change()
466 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= in emulate_monitor_status_change()
468 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= in emulate_monitor_status_change()
Dhandlers.c457 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); in bdw_vgpu_get_dp_bitrate()
521 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); in bdw_vgpu_get_dp_bitrate()
/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c475 MMIO_D(PORT_CLK_SEL(PORT_A)); in iterate_generic_mmio()
476 MMIO_D(PORT_CLK_SEL(PORT_B)); in iterate_generic_mmio()
477 MMIO_D(PORT_CLK_SEL(PORT_C)); in iterate_generic_mmio()
478 MMIO_D(PORT_CLK_SEL(PORT_D)); in iterate_generic_mmio()
479 MMIO_D(PORT_CLK_SEL(PORT_E)); in iterate_generic_mmio()
Di915_reg.h7054 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) macro
7066 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
/drivers/gpu/drm/i915/display/
Dintel_ddi.c1872 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); in hsw_ddi_enable_clock()
1880 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); in hsw_ddi_disable_clock()
1888 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; in hsw_ddi_is_clock_enabled()
1898 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); in hsw_ddi_get_pll()