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Searched refs:PRESCALE_GRPH_CONTROL (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.h44 SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
71 SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
120 uint32_t PRESCALE_GRPH_CONTROL; member
192 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
193 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
194 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
195 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
216 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
217 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
218 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
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Ddce_ipp.c144 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
160 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
213 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_ipp_program_input_lut()
Ddce_ipp.h44 SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
87 IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
171 IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
248 uint32_t PRESCALE_GRPH_CONTROL; member
Ddce_mem_input.c623 REG_UPDATE_4(PRESCALE_GRPH_CONTROL, in program_grph_pixel_format()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c2127 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_v10_0_crtc_load_lut()
Ddce_v11_0.c2168 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_v11_0_crtc_load_lut()