1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /**************************************************************************
3 * Copyright (c) 2007-2011, Intel Corporation.
4 * All Rights Reserved.
5 *
6 **************************************************************************/
7
8 #ifndef _PSB_DRV_H_
9 #define _PSB_DRV_H_
10
11 #include <linux/kref.h>
12 #include <linux/mm_types.h>
13
14 #include <drm/drm_device.h>
15
16 #include "gtt.h"
17 #include "intel_bios.h"
18 #include "mmu.h"
19 #include "oaktrail.h"
20 #include "opregion.h"
21 #include "power.h"
22 #include "psb_intel_drv.h"
23 #include "psb_reg.h"
24
25 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
26
27 #define DRIVER_NAME "gma500"
28 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
29 #define DRIVER_DATE "20140314"
30
31 #define DRIVER_MAJOR 1
32 #define DRIVER_MINOR 0
33 #define DRIVER_PATCHLEVEL 0
34
35 /* Append new drm mode definition here, align with libdrm definition */
36 #define DRM_MODE_SCALE_NO_SCALE 2
37
38 #define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
39 #define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
40 #define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
41
42 /* Hardware offsets */
43 #define PSB_VDC_OFFSET 0x00000000
44 #define PSB_VDC_SIZE 0x000080000
45 #define MRST_MMIO_SIZE 0x0000C0000
46 #define PSB_SGX_SIZE 0x8000
47 #define PSB_SGX_OFFSET 0x00040000
48 #define MRST_SGX_OFFSET 0x00080000
49
50 /* PCI resource identifiers */
51 #define PSB_MMIO_RESOURCE 0
52 #define PSB_AUX_RESOURCE 0
53 #define PSB_GATT_RESOURCE 2
54 #define PSB_GTT_RESOURCE 3
55
56 /* PCI configuration */
57 #define PSB_GMCH_CTRL 0x52
58 #define PSB_BSM 0x5C
59 #define _PSB_GMCH_ENABLED 0x4
60 #define PSB_PGETBL_CTL 0x2020
61 #define _PSB_PGETBL_ENABLED 0x00000001
62 #define PSB_SGX_2D_SLAVE_PORT 0x4000
63 #define PSB_LPC_GBA 0x44
64
65 /* TODO: To get rid of */
66 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
67 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
68
69 /* SGX side MMU definitions (these can probably go) */
70
71 /* Flags for external memory type field */
72 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
73 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
74 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
75
76 /* PTE's and PDE's */
77 #define PSB_PDE_MASK 0x003FFFFF
78 #define PSB_PDE_SHIFT 22
79 #define PSB_PTE_SHIFT 12
80
81 /* Cache control */
82 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
83 #define PSB_PTE_WO 0x0002 /* Write only */
84 #define PSB_PTE_RO 0x0004 /* Read only */
85 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
86
87 /* VDC registers and bits */
88 #define PSB_MSVDX_CLOCKGATING 0x2064
89 #define PSB_TOPAZ_CLOCKGATING 0x2068
90 #define PSB_HWSTAM 0x2098
91 #define PSB_INSTPM 0x20C0
92 #define PSB_INT_IDENTITY_R 0x20A4
93 #define _PSB_IRQ_ASLE (1<<0)
94 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
95 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
96 #define _PSB_DPST_PIPEB_FLAG (1<<4)
97 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
98 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
99 #define _PSB_DPST_PIPEA_FLAG (1<<6)
100 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
101 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
102 #define _PSB_IRQ_DISP_HOTSYNC (1<<17)
103 #define _PSB_IRQ_SGX_FLAG (1<<18)
104 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
105 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
106
107 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
108 _PSB_VSYNC_PIPEB_FLAG)
109
110 #define PSB_INT_IDENTITY_R 0x20A4
111 #define PSB_INT_MASK_R 0x20A8
112 #define PSB_INT_ENABLE_R 0x20A0
113
114 #define _PSB_MMU_ER_MASK 0x0001FF00
115 #define _PSB_MMU_ER_HOST (1 << 16)
116 #define GPIOA 0x5010
117 #define GPIOB 0x5014
118 #define GPIOC 0x5018
119 #define GPIOD 0x501c
120 #define GPIOE 0x5020
121 #define GPIOF 0x5024
122 #define GPIOG 0x5028
123 #define GPIOH 0x502c
124 #define GPIO_CLOCK_DIR_MASK (1 << 0)
125 #define GPIO_CLOCK_DIR_IN (0 << 1)
126 #define GPIO_CLOCK_DIR_OUT (1 << 1)
127 #define GPIO_CLOCK_VAL_MASK (1 << 2)
128 #define GPIO_CLOCK_VAL_OUT (1 << 3)
129 #define GPIO_CLOCK_VAL_IN (1 << 4)
130 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
131 #define GPIO_DATA_DIR_MASK (1 << 8)
132 #define GPIO_DATA_DIR_IN (0 << 9)
133 #define GPIO_DATA_DIR_OUT (1 << 9)
134 #define GPIO_DATA_VAL_MASK (1 << 10)
135 #define GPIO_DATA_VAL_OUT (1 << 11)
136 #define GPIO_DATA_VAL_IN (1 << 12)
137 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
138
139 #define VCLK_DIVISOR_VGA0 0x6000
140 #define VCLK_DIVISOR_VGA1 0x6004
141 #define VCLK_POST_DIV 0x6010
142
143 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
144 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
145 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
146 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
147 #define PSB_COMM_USER_IRQ (1024 >> 2)
148 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
149 #define PSB_COMM_FW (2048 >> 2)
150
151 #define PSB_UIRQ_VISTEST 1
152 #define PSB_UIRQ_OOM_REPLY 2
153 #define PSB_UIRQ_FIRE_TA_REPLY 3
154 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
155
156 #define PSB_2D_SIZE (256*1024*1024)
157 #define PSB_MAX_RELOC_PAGES 1024
158
159 #define PSB_LOW_REG_OFFS 0x0204
160 #define PSB_HIGH_REG_OFFS 0x0600
161
162 #define PSB_NUM_VBLANKS 2
163
164
165 #define PSB_2D_SIZE (256*1024*1024)
166 #define PSB_MAX_RELOC_PAGES 1024
167
168 #define PSB_LOW_REG_OFFS 0x0204
169 #define PSB_HIGH_REG_OFFS 0x0600
170
171 #define PSB_NUM_VBLANKS 2
172 #define PSB_WATCHDOG_DELAY (HZ * 2)
173 #define PSB_LID_DELAY (HZ / 10)
174
175 #define PSB_MAX_BRIGHTNESS 100
176
177 #define PSB_PWR_STATE_ON 1
178 #define PSB_PWR_STATE_OFF 2
179
180 #define PSB_PMPOLICY_NOPM 0
181 #define PSB_PMPOLICY_CLOCKGATING 1
182 #define PSB_PMPOLICY_POWERDOWN 2
183
184 #define PSB_PMSTATE_POWERUP 0
185 #define PSB_PMSTATE_CLOCKGATED 1
186 #define PSB_PMSTATE_POWERDOWN 2
187 #define PSB_PCIx_MSI_ADDR_LOC 0x94
188 #define PSB_PCIx_MSI_DATA_LOC 0x98
189
190 /* Medfield crystal settings */
191 #define KSEL_CRYSTAL_19 1
192 #define KSEL_BYPASS_19 5
193 #define KSEL_BYPASS_25 6
194 #define KSEL_BYPASS_83_100 7
195
196 struct drm_fb_helper;
197
198 struct opregion_header;
199 struct opregion_acpi;
200 struct opregion_swsci;
201 struct opregion_asle;
202
203 struct psb_intel_opregion {
204 struct opregion_header *header;
205 struct opregion_acpi *acpi;
206 struct opregion_swsci *swsci;
207 struct opregion_asle *asle;
208 void *vbt;
209 u32 __iomem *lid_state;
210 struct work_struct asle_work;
211 };
212
213 struct sdvo_device_mapping {
214 u8 initialized;
215 u8 dvo_port;
216 u8 slave_addr;
217 u8 dvo_wiring;
218 u8 i2c_pin;
219 u8 i2c_speed;
220 u8 ddc_pin;
221 };
222
223 struct intel_gmbus {
224 struct i2c_adapter adapter;
225 struct i2c_adapter *force_bit;
226 u32 reg0;
227 };
228
229 /* Register offset maps */
230 struct psb_offset {
231 u32 fp0;
232 u32 fp1;
233 u32 cntr;
234 u32 conf;
235 u32 src;
236 u32 dpll;
237 u32 dpll_md;
238 u32 htotal;
239 u32 hblank;
240 u32 hsync;
241 u32 vtotal;
242 u32 vblank;
243 u32 vsync;
244 u32 stride;
245 u32 size;
246 u32 pos;
247 u32 surf;
248 u32 addr;
249 u32 base;
250 u32 status;
251 u32 linoff;
252 u32 tileoff;
253 u32 palette;
254 };
255
256 /*
257 * Register save state. This is used to hold the context when the
258 * device is powered off. In the case of Oaktrail this can (but does not
259 * yet) include screen blank. Operations occuring during the save
260 * update the register cache instead.
261 */
262
263 /* Common status for pipes */
264 struct psb_pipe {
265 u32 fp0;
266 u32 fp1;
267 u32 cntr;
268 u32 conf;
269 u32 src;
270 u32 dpll;
271 u32 dpll_md;
272 u32 htotal;
273 u32 hblank;
274 u32 hsync;
275 u32 vtotal;
276 u32 vblank;
277 u32 vsync;
278 u32 stride;
279 u32 size;
280 u32 pos;
281 u32 base;
282 u32 surf;
283 u32 addr;
284 u32 status;
285 u32 linoff;
286 u32 tileoff;
287 u32 palette[256];
288 };
289
290 struct psb_state {
291 uint32_t saveVCLK_DIVISOR_VGA0;
292 uint32_t saveVCLK_DIVISOR_VGA1;
293 uint32_t saveVCLK_POST_DIV;
294 uint32_t saveVGACNTRL;
295 uint32_t saveADPA;
296 uint32_t saveLVDS;
297 uint32_t saveDVOA;
298 uint32_t saveDVOB;
299 uint32_t saveDVOC;
300 uint32_t savePP_ON;
301 uint32_t savePP_OFF;
302 uint32_t savePP_CONTROL;
303 uint32_t savePP_CYCLE;
304 uint32_t savePFIT_CONTROL;
305 uint32_t saveCLOCKGATING;
306 uint32_t saveDSPARB;
307 uint32_t savePFIT_AUTO_RATIOS;
308 uint32_t savePFIT_PGM_RATIOS;
309 uint32_t savePP_ON_DELAYS;
310 uint32_t savePP_OFF_DELAYS;
311 uint32_t savePP_DIVISOR;
312 uint32_t saveBCLRPAT_A;
313 uint32_t saveBCLRPAT_B;
314 uint32_t savePERF_MODE;
315 uint32_t saveDSPFW1;
316 uint32_t saveDSPFW2;
317 uint32_t saveDSPFW3;
318 uint32_t saveDSPFW4;
319 uint32_t saveDSPFW5;
320 uint32_t saveDSPFW6;
321 uint32_t saveCHICKENBIT;
322 uint32_t saveDSPACURSOR_CTRL;
323 uint32_t saveDSPBCURSOR_CTRL;
324 uint32_t saveDSPACURSOR_BASE;
325 uint32_t saveDSPBCURSOR_BASE;
326 uint32_t saveDSPACURSOR_POS;
327 uint32_t saveDSPBCURSOR_POS;
328 uint32_t saveOV_OVADD;
329 uint32_t saveOV_OGAMC0;
330 uint32_t saveOV_OGAMC1;
331 uint32_t saveOV_OGAMC2;
332 uint32_t saveOV_OGAMC3;
333 uint32_t saveOV_OGAMC4;
334 uint32_t saveOV_OGAMC5;
335 uint32_t saveOVC_OVADD;
336 uint32_t saveOVC_OGAMC0;
337 uint32_t saveOVC_OGAMC1;
338 uint32_t saveOVC_OGAMC2;
339 uint32_t saveOVC_OGAMC3;
340 uint32_t saveOVC_OGAMC4;
341 uint32_t saveOVC_OGAMC5;
342
343 /* DPST register save */
344 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
345 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
346 uint32_t savePWM_CONTROL_LOGIC;
347 };
348
349 struct cdv_state {
350 uint32_t saveDSPCLK_GATE_D;
351 uint32_t saveRAMCLK_GATE_D;
352 uint32_t saveDSPARB;
353 uint32_t saveDSPFW[6];
354 uint32_t saveADPA;
355 uint32_t savePP_CONTROL;
356 uint32_t savePFIT_PGM_RATIOS;
357 uint32_t saveLVDS;
358 uint32_t savePFIT_CONTROL;
359 uint32_t savePP_ON_DELAYS;
360 uint32_t savePP_OFF_DELAYS;
361 uint32_t savePP_CYCLE;
362 uint32_t saveVGACNTRL;
363 uint32_t saveIER;
364 uint32_t saveIMR;
365 u8 saveLBB;
366 };
367
368 struct psb_save_area {
369 struct psb_pipe pipe[3];
370 uint32_t saveBSM;
371 uint32_t saveVBT;
372 union {
373 struct psb_state psb;
374 struct cdv_state cdv;
375 };
376 uint32_t saveBLC_PWM_CTL2;
377 uint32_t saveBLC_PWM_CTL;
378 };
379
380 struct psb_ops;
381
382 #define PSB_NUM_PIPE 3
383
384 struct intel_scu_ipc_dev;
385
386 struct drm_psb_private {
387 struct drm_device dev;
388
389 struct pci_dev *aux_pdev; /* Currently only used by mrst */
390 struct pci_dev *lpc_pdev; /* Currently only used by mrst */
391 const struct psb_ops *ops;
392 const struct psb_offset *regmap;
393
394 struct child_device_config *child_dev;
395 int child_dev_num;
396
397 struct psb_gtt gtt;
398
399 /* GTT Memory manager */
400 struct psb_gtt_mm *gtt_mm;
401 struct page *scratch_page;
402 u32 __iomem *gtt_map;
403 uint32_t stolen_base;
404 u8 __iomem *vram_addr;
405 unsigned long vram_stolen_size;
406 u16 gmch_ctrl; /* Saved GTT setup */
407 u32 pge_ctl;
408
409 struct mutex gtt_mutex;
410 struct resource *gtt_mem; /* Our PCI resource */
411
412 struct mutex mmap_mutex;
413
414 struct psb_mmu_driver *mmu;
415 struct psb_mmu_pd *pf_pd;
416
417 /* Register base */
418 uint8_t __iomem *sgx_reg;
419 uint8_t __iomem *vdc_reg;
420 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
421 uint16_t lpc_gpio_base;
422 uint32_t gatt_free_offset;
423
424 /* Fencing / irq */
425 uint32_t vdc_irq_mask;
426 uint32_t pipestat[PSB_NUM_PIPE];
427
428 spinlock_t irqmask_lock;
429 bool irq_enabled;
430
431 /* Power */
432 bool pm_initialized;
433
434 /* Modesetting */
435 struct psb_intel_mode_device mode_dev;
436 bool modeset; /* true if we have done the mode_device setup */
437
438 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
439 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
440 uint32_t num_pipe;
441
442 /* OSPM info (Power management base) (TODO: can go ?) */
443 uint32_t ospm_base;
444
445 /* Sizes info */
446 u32 fuse_reg_value;
447 u32 video_device_fuse;
448
449 /* PCI revision ID for B0:D2:F0 */
450 uint8_t platform_rev_id;
451
452 /* gmbus */
453 struct intel_gmbus *gmbus;
454 uint8_t __iomem *gmbus_reg;
455
456 /* Used by SDVO */
457 int crt_ddc_pin;
458 /* FIXME: The mappings should be parsed from bios but for now we can
459 pretend there are no mappings available */
460 struct sdvo_device_mapping sdvo_mappings[2];
461 u32 hotplug_supported_mask;
462 struct drm_property *broadcast_rgb_property;
463 struct drm_property *force_audio_property;
464
465 /* LVDS info */
466 int backlight_duty_cycle; /* restore backlight to this value */
467 bool panel_wants_dither;
468 struct drm_display_mode *panel_fixed_mode;
469 struct drm_display_mode *lfp_lvds_vbt_mode;
470 struct drm_display_mode *sdvo_lvds_vbt_mode;
471
472 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
473 struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
474
475 /* Feature bits from the VBIOS */
476 unsigned int int_tv_support:1;
477 unsigned int lvds_dither:1;
478 unsigned int lvds_vbt:1;
479 unsigned int int_crt_support:1;
480 unsigned int lvds_use_ssc:1;
481 int lvds_ssc_freq;
482 bool is_lvds_on;
483 bool is_mipi_on;
484 bool lvds_enabled_in_vbt;
485 u32 mipi_ctrl_display;
486
487 unsigned int core_freq;
488 uint32_t iLVDS_enable;
489
490 /* MID specific */
491 bool use_msi;
492 bool has_gct;
493 struct oaktrail_gct_data gct_data;
494
495 /* Oaktrail HDMI state */
496 struct oaktrail_hdmi_dev *hdmi_priv;
497
498 /* Register state */
499 struct psb_save_area regs;
500
501 /* Hotplug handling */
502 struct work_struct hotplug_work;
503
504 /* LID-Switch */
505 spinlock_t lid_lock;
506 struct timer_list lid_timer;
507 struct psb_intel_opregion opregion;
508 u32 lid_last_state;
509
510 /* Watchdog */
511 uint32_t apm_reg;
512 uint16_t apm_base;
513
514 /*
515 * Used for modifying backlight from
516 * xrandr -- consider removing and using HAL instead
517 */
518 struct intel_scu_ipc_dev *scu;
519 struct backlight_device *backlight_device;
520 struct drm_property *backlight_property;
521 bool backlight_enabled;
522 int backlight_level;
523 uint32_t blc_adj1;
524 uint32_t blc_adj2;
525
526 struct drm_fb_helper *fb_helper;
527
528 bool dsr_enable;
529 u32 dsr_fb_update;
530 bool dpi_panel_on[3];
531 void *dsi_configs[2];
532 u32 bpp;
533 u32 bpp2;
534
535 u32 pipeconf[3];
536 u32 dspcntr[3];
537
538 bool dplla_96mhz; /* DPLL data from the VBT */
539
540 struct {
541 int rate;
542 int lanes;
543 int preemphasis;
544 int vswing;
545
546 bool initialized;
547 bool support;
548 int bpp;
549 struct edp_power_seq pps;
550 } edp;
551 uint8_t panel_type;
552 };
553
to_drm_psb_private(struct drm_device * dev)554 static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev)
555 {
556 return container_of(dev, struct drm_psb_private, dev);
557 }
558
559 /* Operations for each board type */
560 struct psb_ops {
561 const char *name;
562 int pipes; /* Number of output pipes */
563 int crtcs; /* Number of CRTCs */
564 int sgx_offset; /* Base offset of SGX device */
565 int hdmi_mask; /* Mask of HDMI CRTCs */
566 int lvds_mask; /* Mask of LVDS CRTCs */
567 int sdvo_mask; /* Mask of SDVO CRTCs */
568 int cursor_needs_phys; /* If cursor base reg need physical address */
569
570 /* Sub functions */
571 struct drm_crtc_helper_funcs const *crtc_helper;
572 const struct gma_clock_funcs *clock_funcs;
573
574 /* Setup hooks */
575 int (*chip_setup)(struct drm_device *dev);
576 void (*chip_teardown)(struct drm_device *dev);
577 /* Optional helper caller after modeset */
578 void (*errata)(struct drm_device *dev);
579
580 /* Display management hooks */
581 int (*output_init)(struct drm_device *dev);
582 int (*hotplug)(struct drm_device *dev);
583 void (*hotplug_enable)(struct drm_device *dev, bool on);
584 /* Power management hooks */
585 void (*init_pm)(struct drm_device *dev);
586 int (*save_regs)(struct drm_device *dev);
587 int (*restore_regs)(struct drm_device *dev);
588 void (*save_crtc)(struct drm_crtc *crtc);
589 void (*restore_crtc)(struct drm_crtc *crtc);
590 int (*power_up)(struct drm_device *dev);
591 int (*power_down)(struct drm_device *dev);
592 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
593 void (*disable_sr)(struct drm_device *dev);
594
595 void (*lvds_bl_power)(struct drm_device *dev, bool on);
596
597 /* Backlight */
598 int (*backlight_init)(struct drm_device *dev);
599 void (*backlight_set)(struct drm_device *dev, int level);
600 int (*backlight_get)(struct drm_device *dev);
601 const char *backlight_name;
602
603 int i2c_bus; /* I2C bus identifier for Moorestown */
604 };
605
606 /* psb_lid.c */
607 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
608 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
609
610 /* modesetting */
611 extern void psb_modeset_init(struct drm_device *dev);
612 extern void psb_modeset_cleanup(struct drm_device *dev);
613 extern int psb_fbdev_init(struct drm_device *dev);
614
615 /* backlight.c */
616 int gma_backlight_init(struct drm_device *dev);
617 void gma_backlight_exit(struct drm_device *dev);
618 void gma_backlight_disable(struct drm_device *dev);
619 void gma_backlight_enable(struct drm_device *dev);
620 void gma_backlight_set(struct drm_device *dev, int v);
621
622 /* oaktrail_crtc.c */
623 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
624
625 /* oaktrail_lvds.c */
626 extern void oaktrail_lvds_init(struct drm_device *dev,
627 struct psb_intel_mode_device *mode_dev);
628
629 /* psb_intel_display.c */
630 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
631
632 /* psb_intel_lvds.c */
633 extern const struct drm_connector_helper_funcs
634 psb_intel_lvds_connector_helper_funcs;
635 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
636
637 /* gem.c */
638 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
639 struct drm_mode_create_dumb *args);
640
641 /* psb_device.c */
642 extern const struct psb_ops psb_chip_ops;
643
644 /* oaktrail_device.c */
645 extern const struct psb_ops oaktrail_chip_ops;
646
647 /* cdv_device.c */
648 extern const struct psb_ops cdv_chip_ops;
649
650 /* Utilities */
REGISTER_READ(struct drm_device * dev,uint32_t reg)651 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
652 {
653 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
654 return ioread32(dev_priv->vdc_reg + reg);
655 }
656
REGISTER_READ_AUX(struct drm_device * dev,uint32_t reg)657 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
658 {
659 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
660 return ioread32(dev_priv->aux_reg + reg);
661 }
662
663 #define REG_READ(reg) REGISTER_READ(dev, (reg))
664 #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
665
666 /* Useful for post reads */
REGISTER_READ_WITH_AUX(struct drm_device * dev,uint32_t reg,int aux)667 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
668 uint32_t reg, int aux)
669 {
670 uint32_t val;
671
672 if (aux)
673 val = REG_READ_AUX(reg);
674 else
675 val = REG_READ(reg);
676
677 return val;
678 }
679
680 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
681
REGISTER_WRITE(struct drm_device * dev,uint32_t reg,uint32_t val)682 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
683 uint32_t val)
684 {
685 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
686 iowrite32((val), dev_priv->vdc_reg + (reg));
687 }
688
REGISTER_WRITE_AUX(struct drm_device * dev,uint32_t reg,uint32_t val)689 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
690 uint32_t val)
691 {
692 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
693 iowrite32((val), dev_priv->aux_reg + (reg));
694 }
695
696 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
697 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
698
REGISTER_WRITE_WITH_AUX(struct drm_device * dev,uint32_t reg,uint32_t val,int aux)699 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
700 uint32_t val, int aux)
701 {
702 if (aux)
703 REG_WRITE_AUX(reg, val);
704 else
705 REG_WRITE(reg, val);
706 }
707
708 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
709
REGISTER_WRITE16(struct drm_device * dev,uint32_t reg,uint32_t val)710 static inline void REGISTER_WRITE16(struct drm_device *dev,
711 uint32_t reg, uint32_t val)
712 {
713 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
714 iowrite16((val), dev_priv->vdc_reg + (reg));
715 }
716
717 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
718
REGISTER_WRITE8(struct drm_device * dev,uint32_t reg,uint32_t val)719 static inline void REGISTER_WRITE8(struct drm_device *dev,
720 uint32_t reg, uint32_t val)
721 {
722 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
723 iowrite8((val), dev_priv->vdc_reg + (reg));
724 }
725
726 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
727
728 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
729 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
730
731 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
732 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
733
734 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
735 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
736
737 #endif
738