1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
5 */
6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
8 #include "msm_drv.h"
9 #include "dpu_kms.h"
10 #include "dpu_hw_mdss.h"
11 #include "dpu_hw_util.h"
12
13 /* using a file static variables for debugfs access */
14 static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE;
15
16 /* DPU_SCALER_QSEED3 */
17 #define QSEED3_HW_VERSION 0x00
18 #define QSEED3_OP_MODE 0x04
19 #define QSEED3_RGB2Y_COEFF 0x08
20 #define QSEED3_PHASE_INIT 0x0C
21 #define QSEED3_PHASE_STEP_Y_H 0x10
22 #define QSEED3_PHASE_STEP_Y_V 0x14
23 #define QSEED3_PHASE_STEP_UV_H 0x18
24 #define QSEED3_PHASE_STEP_UV_V 0x1C
25 #define QSEED3_PRELOAD 0x20
26 #define QSEED3_DE_SHARPEN 0x24
27 #define QSEED3_DE_SHARPEN_CTL 0x28
28 #define QSEED3_DE_SHAPE_CTL 0x2C
29 #define QSEED3_DE_THRESHOLD 0x30
30 #define QSEED3_DE_ADJUST_DATA_0 0x34
31 #define QSEED3_DE_ADJUST_DATA_1 0x38
32 #define QSEED3_DE_ADJUST_DATA_2 0x3C
33 #define QSEED3_SRC_SIZE_Y_RGB_A 0x40
34 #define QSEED3_SRC_SIZE_UV 0x44
35 #define QSEED3_DST_SIZE 0x48
36 #define QSEED3_COEF_LUT_CTRL 0x4C
37 #define QSEED3_COEF_LUT_SWAP_BIT 0
38 #define QSEED3_COEF_LUT_DIR_BIT 1
39 #define QSEED3_COEF_LUT_Y_CIR_BIT 2
40 #define QSEED3_COEF_LUT_UV_CIR_BIT 3
41 #define QSEED3_COEF_LUT_Y_SEP_BIT 4
42 #define QSEED3_COEF_LUT_UV_SEP_BIT 5
43 #define QSEED3_BUFFER_CTRL 0x50
44 #define QSEED3_CLK_CTRL0 0x54
45 #define QSEED3_CLK_CTRL1 0x58
46 #define QSEED3_CLK_STATUS 0x5C
47 #define QSEED3_PHASE_INIT_Y_H 0x90
48 #define QSEED3_PHASE_INIT_Y_V 0x94
49 #define QSEED3_PHASE_INIT_UV_H 0x98
50 #define QSEED3_PHASE_INIT_UV_V 0x9C
51 #define QSEED3_COEF_LUT 0x100
52 #define QSEED3_FILTERS 5
53 #define QSEED3_LUT_REGIONS 4
54 #define QSEED3_CIRCULAR_LUTS 9
55 #define QSEED3_SEPARABLE_LUTS 10
56 #define QSEED3_LUT_SIZE 60
57 #define QSEED3_ENABLE 2
58 #define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32))
59 #define QSEED3_CIR_LUT_SIZE \
60 (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
61 #define QSEED3_SEP_LUT_SIZE \
62 (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
63
64 /* DPU_SCALER_QSEED3LITE */
65 #define QSEED3LITE_COEF_LUT_Y_SEP_BIT 4
66 #define QSEED3LITE_COEF_LUT_UV_SEP_BIT 5
67 #define QSEED3LITE_COEF_LUT_CTRL 0x4C
68 #define QSEED3LITE_COEF_LUT_SWAP_BIT 0
69 #define QSEED3LITE_DIR_FILTER_WEIGHT 0x60
70 #define QSEED3LITE_FILTERS 2
71 #define QSEED3LITE_SEPARABLE_LUTS 10
72 #define QSEED3LITE_LUT_SIZE 33
73 #define QSEED3LITE_SEP_LUT_SIZE \
74 (QSEED3LITE_LUT_SIZE * QSEED3LITE_SEPARABLE_LUTS * sizeof(u32))
75
76
dpu_reg_write(struct dpu_hw_blk_reg_map * c,u32 reg_off,u32 val,const char * name)77 void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
78 u32 reg_off,
79 u32 val,
80 const char *name)
81 {
82 /* don't need to mutex protect this */
83 if (c->log_mask & dpu_hw_util_log_mask)
84 DPU_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n",
85 name, reg_off, val);
86 writel_relaxed(val, c->blk_addr + reg_off);
87 }
88
dpu_reg_read(struct dpu_hw_blk_reg_map * c,u32 reg_off)89 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off)
90 {
91 return readl_relaxed(c->blk_addr + reg_off);
92 }
93
dpu_hw_util_get_log_mask_ptr(void)94 u32 *dpu_hw_util_get_log_mask_ptr(void)
95 {
96 return &dpu_hw_util_log_mask;
97 }
98
_dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map * c,struct dpu_hw_scaler3_cfg * scaler3_cfg,u32 offset)99 static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c,
100 struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset)
101 {
102 int i, j, filter;
103 int config_lut = 0x0;
104 unsigned long lut_flags;
105 u32 lut_addr, lut_offset, lut_len;
106 u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
107 static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
108 {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
109 {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
110 {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
111 {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
112 {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
113 };
114
115 lut_flags = (unsigned long) scaler3_cfg->lut_flag;
116 if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
117 (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
118 lut[0] = scaler3_cfg->dir_lut;
119 config_lut = 1;
120 }
121 if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
122 (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
123 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
124 lut[1] = scaler3_cfg->cir_lut +
125 scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
126 config_lut = 1;
127 }
128 if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
129 (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
130 (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
131 lut[2] = scaler3_cfg->cir_lut +
132 scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
133 config_lut = 1;
134 }
135 if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
136 (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
137 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
138 lut[3] = scaler3_cfg->sep_lut +
139 scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
140 config_lut = 1;
141 }
142 if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
143 (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
144 (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
145 lut[4] = scaler3_cfg->sep_lut +
146 scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
147 config_lut = 1;
148 }
149
150 if (config_lut) {
151 for (filter = 0; filter < QSEED3_FILTERS; filter++) {
152 if (!lut[filter])
153 continue;
154 lut_offset = 0;
155 for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
156 lut_addr = QSEED3_COEF_LUT + offset
157 + off_tbl[filter][i][1];
158 lut_len = off_tbl[filter][i][0] << 2;
159 for (j = 0; j < lut_len; j++) {
160 DPU_REG_WRITE(c,
161 lut_addr,
162 (lut[filter])[lut_offset++]);
163 lut_addr += 4;
164 }
165 }
166 }
167 }
168
169 if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
170 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));
171
172 }
173
_dpu_hw_setup_scaler3lite_lut(struct dpu_hw_blk_reg_map * c,struct dpu_hw_scaler3_cfg * scaler3_cfg,u32 offset)174 static void _dpu_hw_setup_scaler3lite_lut(struct dpu_hw_blk_reg_map *c,
175 struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset)
176 {
177 int j, filter;
178 int config_lut = 0x0;
179 unsigned long lut_flags;
180 u32 lut_addr, lut_offset;
181 u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL};
182 static const uint32_t off_tbl[QSEED3_FILTERS] = { 0x000, 0x200 };
183
184 DPU_REG_WRITE(c, QSEED3LITE_DIR_FILTER_WEIGHT + offset, scaler3_cfg->dir_weight);
185
186 if (!scaler3_cfg->sep_lut)
187 return;
188
189 lut_flags = (unsigned long) scaler3_cfg->lut_flag;
190 if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
191 (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3LITE_SEPARABLE_LUTS) &&
192 (scaler3_cfg->sep_len == QSEED3LITE_SEP_LUT_SIZE)) {
193 lut[0] = scaler3_cfg->sep_lut +
194 scaler3_cfg->y_rgb_sep_lut_idx * QSEED3LITE_LUT_SIZE;
195 config_lut = 1;
196 }
197 if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
198 (scaler3_cfg->uv_sep_lut_idx < QSEED3LITE_SEPARABLE_LUTS) &&
199 (scaler3_cfg->sep_len == QSEED3LITE_SEP_LUT_SIZE)) {
200 lut[1] = scaler3_cfg->sep_lut +
201 scaler3_cfg->uv_sep_lut_idx * QSEED3LITE_LUT_SIZE;
202 config_lut = 1;
203 }
204
205 if (config_lut) {
206 for (filter = 0; filter < QSEED3LITE_FILTERS; filter++) {
207 if (!lut[filter])
208 continue;
209 lut_offset = 0;
210 lut_addr = QSEED3_COEF_LUT + offset + off_tbl[filter];
211 for (j = 0; j < QSEED3LITE_LUT_SIZE; j++) {
212 DPU_REG_WRITE(c,
213 lut_addr,
214 (lut[filter])[lut_offset++]);
215 lut_addr += 4;
216 }
217 }
218 }
219
220 if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
221 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));
222
223 }
224
_dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map * c,struct dpu_hw_scaler3_de_cfg * de_cfg,u32 offset)225 static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c,
226 struct dpu_hw_scaler3_de_cfg *de_cfg, u32 offset)
227 {
228 u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
229 u32 adjust_a, adjust_b, adjust_c;
230
231 if (!de_cfg->enable)
232 return;
233
234 sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
235 ((de_cfg->sharpen_level2 & 0x1FF) << 16);
236
237 sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
238 ((de_cfg->prec_shift & 0x7) << 13) |
239 ((de_cfg->clip & 0x7) << 16);
240
241 shape_ctl = (de_cfg->thr_quiet & 0xFF) |
242 ((de_cfg->thr_dieout & 0x3FF) << 16);
243
244 de_thr = (de_cfg->thr_low & 0x3FF) |
245 ((de_cfg->thr_high & 0x3FF) << 16);
246
247 adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
248 ((de_cfg->adjust_a[1] & 0x3FF) << 10) |
249 ((de_cfg->adjust_a[2] & 0x3FF) << 20);
250
251 adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
252 ((de_cfg->adjust_b[1] & 0x3FF) << 10) |
253 ((de_cfg->adjust_b[2] & 0x3FF) << 20);
254
255 adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
256 ((de_cfg->adjust_c[1] & 0x3FF) << 10) |
257 ((de_cfg->adjust_c[2] & 0x3FF) << 20);
258
259 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl);
260 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl);
261 DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl);
262 DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr);
263 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a);
264 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b);
265 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c);
266
267 }
268
dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map * c,struct dpu_hw_scaler3_cfg * scaler3_cfg,u32 scaler_offset,u32 scaler_version,const struct dpu_format * format)269 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
270 struct dpu_hw_scaler3_cfg *scaler3_cfg,
271 u32 scaler_offset, u32 scaler_version,
272 const struct dpu_format *format)
273 {
274 u32 op_mode = 0;
275 u32 phase_init, preload, src_y_rgb, src_uv, dst;
276
277 if (!scaler3_cfg->enable)
278 goto end;
279
280 op_mode |= BIT(0);
281 op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
282
283 if (format && DPU_FORMAT_IS_YUV(format)) {
284 op_mode |= BIT(12);
285 op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
286 }
287
288 op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
289 op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
290
291 preload =
292 ((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
293 ((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
294 ((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
295 ((scaler3_cfg->preload_y[1] & 0x7F) << 24);
296
297 src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
298 ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
299
300 src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
301 ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
302
303 dst = (scaler3_cfg->dst_width & 0x1FFFF) |
304 ((scaler3_cfg->dst_height & 0x1FFFF) << 16);
305
306 if (scaler3_cfg->de.enable) {
307 _dpu_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset);
308 op_mode |= BIT(8);
309 }
310
311 if (scaler3_cfg->lut_flag) {
312 if (scaler_version < 0x2004)
313 _dpu_hw_setup_scaler3_lut(c, scaler3_cfg, scaler_offset);
314 else
315 _dpu_hw_setup_scaler3lite_lut(c, scaler3_cfg, scaler_offset);
316 }
317
318 if (scaler_version == 0x1002) {
319 phase_init =
320 ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
321 ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
322 ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
323 ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
324 DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init);
325 } else {
326 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset,
327 scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
328 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset,
329 scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
330 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset,
331 scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
332 DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset,
333 scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
334 }
335
336 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset,
337 scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
338
339 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset,
340 scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
341
342 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset,
343 scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
344
345 DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset,
346 scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
347
348 DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload);
349
350 DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb);
351
352 DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv);
353
354 DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
355
356 end:
357 if (format && !DPU_FORMAT_IS_DX(format))
358 op_mode |= BIT(14);
359
360 if (format && format->alpha_enable) {
361 op_mode |= BIT(10);
362 if (scaler_version == 0x1002)
363 op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
364 else
365 op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
366 }
367
368 DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);
369 }
370
dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map * c,u32 scaler_offset)371 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
372 u32 scaler_offset)
373 {
374 return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);
375 }
376
dpu_hw_csc_setup(struct dpu_hw_blk_reg_map * c,u32 csc_reg_off,const struct dpu_csc_cfg * data,bool csc10)377 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
378 u32 csc_reg_off,
379 const struct dpu_csc_cfg *data, bool csc10)
380 {
381 static const u32 matrix_shift = 7;
382 u32 clamp_shift = csc10 ? 16 : 8;
383 u32 val;
384
385 /* matrix coeff - convert S15.16 to S4.9 */
386 val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) |
387 (((data->csc_mv[1] >> matrix_shift) & 0x1FFF) << 16);
388 DPU_REG_WRITE(c, csc_reg_off, val);
389 val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) |
390 (((data->csc_mv[3] >> matrix_shift) & 0x1FFF) << 16);
391 DPU_REG_WRITE(c, csc_reg_off + 0x4, val);
392 val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) |
393 (((data->csc_mv[5] >> matrix_shift) & 0x1FFF) << 16);
394 DPU_REG_WRITE(c, csc_reg_off + 0x8, val);
395 val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) |
396 (((data->csc_mv[7] >> matrix_shift) & 0x1FFF) << 16);
397 DPU_REG_WRITE(c, csc_reg_off + 0xc, val);
398 val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF;
399 DPU_REG_WRITE(c, csc_reg_off + 0x10, val);
400
401 /* Pre clamp */
402 val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1];
403 DPU_REG_WRITE(c, csc_reg_off + 0x14, val);
404 val = (data->csc_pre_lv[2] << clamp_shift) | data->csc_pre_lv[3];
405 DPU_REG_WRITE(c, csc_reg_off + 0x18, val);
406 val = (data->csc_pre_lv[4] << clamp_shift) | data->csc_pre_lv[5];
407 DPU_REG_WRITE(c, csc_reg_off + 0x1c, val);
408
409 /* Post clamp */
410 val = (data->csc_post_lv[0] << clamp_shift) | data->csc_post_lv[1];
411 DPU_REG_WRITE(c, csc_reg_off + 0x20, val);
412 val = (data->csc_post_lv[2] << clamp_shift) | data->csc_post_lv[3];
413 DPU_REG_WRITE(c, csc_reg_off + 0x24, val);
414 val = (data->csc_post_lv[4] << clamp_shift) | data->csc_post_lv[5];
415 DPU_REG_WRITE(c, csc_reg_off + 0x28, val);
416
417 /* Pre-Bias */
418 DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]);
419 DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]);
420 DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]);
421
422 /* Post-Bias */
423 DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]);
424 DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
425 DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
426 }
427
428 /**
429 * _dpu_hw_get_qos_lut - get LUT mapping based on fill level
430 * @tbl: Pointer to LUT table
431 * @total_fl: fill level
432 * Return: LUT setting corresponding to the fill level
433 */
_dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl * tbl,u32 total_fl)434 u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
435 u32 total_fl)
436 {
437 int i;
438
439 if (!tbl || !tbl->nentry || !tbl->entries)
440 return 0;
441
442 for (i = 0; i < tbl->nentry; i++)
443 if (total_fl <= tbl->entries[i].fl)
444 return tbl->entries[i].lut;
445
446 /* if last fl is zero, use as default */
447 if (!tbl->entries[i-1].fl)
448 return tbl->entries[i-1].lut;
449
450 return 0;
451 }
452
453 /*
454 * note: Aside from encoders, input_sel should be set to 0x0 by default
455 */
dpu_hw_setup_misr(struct dpu_hw_blk_reg_map * c,u32 misr_ctrl_offset,u8 input_sel)456 void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
457 u32 misr_ctrl_offset, u8 input_sel)
458 {
459 u32 config = 0;
460
461 DPU_REG_WRITE(c, misr_ctrl_offset, MISR_CTRL_STATUS_CLEAR);
462
463 /* Clear old MISR value (in case it's read before a new value is calculated)*/
464 wmb();
465
466 config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
467 ((input_sel & 0xF) << 24);
468 DPU_REG_WRITE(c, misr_ctrl_offset, config);
469 }
470
dpu_hw_collect_misr(struct dpu_hw_blk_reg_map * c,u32 misr_ctrl_offset,u32 misr_signature_offset,u32 * misr_value)471 int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
472 u32 misr_ctrl_offset,
473 u32 misr_signature_offset,
474 u32 *misr_value)
475 {
476 u32 ctrl = 0;
477
478 if (!misr_value)
479 return -EINVAL;
480
481 ctrl = DPU_REG_READ(c, misr_ctrl_offset);
482
483 if (!(ctrl & MISR_CTRL_ENABLE))
484 return -ENODATA;
485
486 if (!(ctrl & MISR_CTRL_STATUS))
487 return -EINVAL;
488
489 *misr_value = DPU_REG_READ(c, misr_signature_offset);
490
491 return 0;
492 }
493