Searched refs:REG_AXXX_CP_RB_WPTR (Results 1 – 3 of 3) sorted by relevance
51 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()97 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
82 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()108 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
254 #define REG_AXXX_CP_RB_WPTR 0x000001c5 macro