| /drivers/spi/ |
| D | spi-microchip-core-qspi.c | 93 #define REG_STATUS (0x10) macro
178 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) in mchp_coreqspi_read_op()
190 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) in mchp_coreqspi_read_op()
206 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) in mchp_coreqspi_write_op()
218 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) in mchp_coreqspi_write_op()
243 int intfield = readl_relaxed(qspi->regs + REG_STATUS) & STATUS_MASK; in mchp_coreqspi_isr()
249 writel_relaxed(IEN_TXDONE, qspi->regs + REG_STATUS); in mchp_coreqspi_isr()
254 writel_relaxed(IEN_RXAVAILABLE, qspi->regs + REG_STATUS); in mchp_coreqspi_isr()
260 writel_relaxed(IEN_RXDONE, qspi->regs + REG_STATUS); in mchp_coreqspi_isr()
375 ret = readl_poll_timeout(qspi->regs + REG_STATUS, status, in mchp_qspi_wait_for_ready()
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| D | spi-microchip-core.c | 78 #define REG_STATUS (0x08) macro
147 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) { in mchp_corespi_read_fifo()
226 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) { in mchp_corespi_write_fifo()
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| D | spi-meson-spifc.c | 26 #define REG_STATUS 0x10 macro
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| /drivers/hwmon/ |
| D | max31760.c | 23 #define REG_STATUS 0x5A macro
91 ret = regmap_read(state->regmap, REG_STATUS, ®val); in max31760_read()
99 ret = regmap_read(state->regmap, REG_STATUS, ®val); in max31760_read()
110 ret = regmap_read(state->regmap, REG_STATUS, ®val); in max31760_read()
153 ret = regmap_read(state->regmap, REG_STATUS, ®val); in max31760_read()
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| /drivers/net/ethernet/seeq/ |
| D | ether3.c | 122 while ((ether3_inw(REG_STATUS) & STAT_FIFOEMPTY) == 0) { in ether3_setbuffer()
328 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_init_for_open()
422 while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON)) in ether3_close()
462 ether3_inw(REG_STATUS), ether3_inw(REG_CONFIG1), ether3_inw(REG_CONFIG2)); in ether3_timeout()
529 if (!(ether3_inw(REG_STATUS) & STAT_TXON)) { in ether3_sendpacket()
557 status = ether3_inw(REG_STATUS); in ether3_interrupt()
673 if (!(ether3_inw(REG_STATUS) & STAT_RXON)) { in ether3_rx()
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| D | ether3.h | 44 #define REG_STATUS (priv(dev)->seeq + 0x0000) macro
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| /drivers/media/dvb-frontends/ |
| D | lgs8gl5.c | 38 #define REG_STATUS 0xa4 macro
205 val = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_start_demod()
244 u8 flags = lgs8gl5_read_reg(state, REG_STATUS); in lgs8gl5_read_status()
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| /drivers/media/spi/ |
| D | gs1662.c | 26 #define REG_STATUS 0x04 macro
310 gs_read_register(gs->pdev, REG_STATUS, ®_value); in gs_query_dv_timings()
383 ret = gs_read_register(gs->pdev, REG_STATUS, ®_value); in gs_g_input_status()
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| /drivers/mmc/host/ |
| D | moxart-mmc.c | 46 #define REG_STATUS 40 macro
187 *status = readl(host->base + REG_STATUS); in moxart_wait_for_status()
401 if (readl(host->base + REG_STATUS) & CARD_DETECT) { in moxart_request()
463 status = readl(host->base + REG_STATUS); in moxart_irq()
534 return !!(readl(host->base + REG_STATUS) & WRITE_PROT); in moxart_get_ro()
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| /drivers/media/tuners/ |
| D | max2165_priv.h | 28 #define REG_STATUS 0x11 macro
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| D | max2165.c | 226 max2165_read_reg(priv, REG_STATUS, &status); in max2165_debug_status()
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| /drivers/net/usb/ |
| D | net1080.c | 87 #define REG_STATUS ((u8)0x11) macro
267 if ((retval = nc_register_read(dev, REG_STATUS, &vp)) < 0) { in net1080_reset()
310 retval = nc_register_read(dev, REG_STATUS, &vp); in net1080_check_connect()
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| /drivers/pwm/ |
| D | pwm-vt8500.c | 35 #define REG_STATUS 0x40 macro
64 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) in vt8500_pwm_busy_wait()
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| /drivers/input/touchscreen/ |
| D | st1232.c | 29 #define REG_STATUS 0x01 /* Device Status | Error Code */ macro
96 error = st1232_ts_read_data(ts, REG_STATUS, 1); in st1232_ts_wait_ready()
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| /drivers/power/supply/ |
| D | sbs-battery.c | 37 REG_STATUS, enumerator
133 [REG_STATUS] =
586 ret = sbs_read_word_data(client, sbs_data[REG_STATUS].addr); in sbs_get_battery_presence_and_health()
1079 ret = sbs_read_word_data(chip->client, sbs_data[REG_STATUS].addr); in sbs_delayed_work()
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| /drivers/crypto/qce/ |
| D | regs-v5.h | 12 #define REG_STATUS 0x100 macro
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| D | common.c | 88 qce_write(qce, REG_STATUS, 0); in qce_setup_config()
570 *status = qce_read(qce, REG_STATUS); in qce_check_status()
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| /drivers/media/i2c/s5c73m3/ |
| D | s5c73m3.h | 72 #define REG_STATUS S5C73M3_REG(0x0009, 0x5080) macro
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| D | s5c73m3-core.c | 248 ret = s5c73m3_read(state, REG_STATUS, &status); in s5c73m3_check_status()
293 return s5c73m3_write(state, REG_STATUS, 0x0001); in s5c73m3_isp_command()
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| /drivers/usb/storage/ |
| D | isd200.c | 143 #define REG_STATUS 0x80 macro
501 REG_STATUS | REG_ERROR; in isd200_action()
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| /drivers/mtd/nand/spi/ |
| D | core.c | 48 return spinand_read_reg_op(spinand, REG_STATUS, status); in spinand_read_status()
504 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(REG_STATUS, in spinand_wait()
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| /drivers/block/paride/ |
| D | ppc6lnx.c | 51 #define REG_STATUS 0x00 // status register macro
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