1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __RTL8188E_XMIT_H__ 5 #define __RTL8188E_XMIT_H__ 6 7 #define MAX_TX_AGG_PACKET_NUMBER 0xFF 8 /* */ 9 /* Queue Select Value in TxDesc */ 10 /* */ 11 #define QSLT_BK 0x2/* 0x01 */ 12 #define QSLT_BE 0x0 13 #define QSLT_VI 0x5/* 0x4 */ 14 #define QSLT_VO 0x7/* 0x6 */ 15 #define QSLT_BEACON 0x10 16 #define QSLT_HIGH 0x11 17 #define QSLT_MGNT 0x12 18 #define QSLT_CMD 0x13 19 20 /* For 88e early mode */ 21 #define SET_EARLYMODE_PKTNUM(__paddr, __value) \ 22 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(2, 0)) 23 #define SET_EARLYMODE_LEN0(__pAddr, __Value) \ 24 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(15, 4)) 25 #define SET_EARLYMODE_LEN1(__paddr, __value) \ 26 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(27, 16)) 27 #define SET_EARLYMODE_LEN2_1(__pdr, __vValue) \ 28 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(31, 28)) 29 #define SET_EARLYMODE_LEN2_2(__paddr, __value) \ 30 le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(7, 0)) 31 #define SET_EARLYMODE_LEN3(__pAddr, __Value) \ 32 le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(19, 8)) 33 #define SET_EARLYMODE_LEN4(__paAddr, __vValue) \ 34 le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(31, 20)) 35 36 /* defined for TX DESC Operation */ 37 38 #define MAX_TID (15) 39 40 /* OFFSET 0 */ 41 #define OFFSET_SZ 0 42 #define OFFSET_SHT 16 43 #define BMC BIT(24) 44 #define LSG BIT(26) 45 #define FSG BIT(27) 46 #define OWN BIT(31) 47 48 /* OFFSET 4 */ 49 #define PKT_OFFSET_SZ 0 50 #define QSEL_SHT 8 51 #define RATE_ID_SHT 16 52 #define NAVUSEHDR BIT(20) 53 #define SEC_TYPE_SHT 22 54 #define PKT_OFFSET_SHT 26 55 56 /* OFFSET 8 */ 57 #define AGG_EN BIT(12) 58 #define AGG_BK BIT(16) 59 #define AMPDU_DENSITY_SHT 20 60 #define ANTSEL_A BIT(24) 61 #define ANTSEL_B BIT(25) 62 #define TX_ANT_CCK_SHT 26 63 #define TX_ANTL_SHT 28 64 #define TX_ANT_HT_SHT 30 65 66 /* OFFSET 12 */ 67 #define SEQ_SHT 16 68 #define EN_HWSEQ BIT(31) 69 70 /* OFFSET 16 */ 71 #define QOS BIT(6) 72 #define HW_SSN BIT(7) 73 #define USERATE BIT(8) 74 #define DISDATAFB BIT(10) 75 #define CTS_2_SELF BIT(11) 76 #define RTS_EN BIT(12) 77 #define HW_RTS_EN BIT(13) 78 #define DATA_SHORT BIT(24) 79 #define PWR_STATUS_SHT 15 80 #define DATA_SC_SHT 20 81 #define DATA_BW BIT(25) 82 83 /* OFFSET 20 */ 84 #define RTY_LMT_EN BIT(17) 85 86 /* OFFSET 20 */ 87 #define SGI BIT(6) 88 #define USB_TXAGG_NUM_SHT 24 89 90 #define USB_TXAGG_DESC_NUM 0x6 91 92 #define txdesc_set_ccx_sw_88e(txdesc, value) \ 93 do { \ 94 ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \ 95 ((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \ 96 } while (0) 97 98 struct txrpt_ccx_88e { 99 /* offset 0 */ 100 u8 tag1:1; 101 u8 pkt_num:3; 102 u8 txdma_underflow:1; 103 u8 int_bt:1; 104 u8 int_tri:1; 105 u8 int_ccx:1; 106 107 /* offset 1 */ 108 u8 mac_id:6; 109 u8 pkt_ok:1; 110 u8 bmc:1; 111 112 /* offset 2 */ 113 u8 retry_cnt:6; 114 u8 lifetime_over:1; 115 u8 retry_over:1; 116 117 /* offset 3 */ 118 u8 ccx_qtime0; 119 u8 ccx_qtime1; 120 121 /* offset 5 */ 122 u8 final_data_rate; 123 124 /* offset 6 */ 125 u8 sw1:4; 126 u8 qsel:4; 127 128 /* offset 7 */ 129 u8 sw0; 130 }; 131 132 void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc, 133 u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); 134 s32 rtl8188eu_init_xmit_priv(struct adapter *padapter); 135 s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *frame); 136 s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *frame); 137 s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter); 138 #define hal_xmit_handler rtl8188eu_xmit_buf_handler 139 void rtl8188eu_xmit_tasklet(unsigned long priv); 140 bool rtl8188eu_xmitframe_complete(struct adapter *padapter, 141 struct xmit_priv *pxmitpriv, 142 struct xmit_buf *pxmitbuf); 143 144 #endif /* __RTL8188E_XMIT_H__ */ 145