Home
last modified time | relevance | path

Searched refs:SOCFPGA_PLL_DIVF_MASK (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/socfpga/
Dclk-pll-a10.c21 #define SOCFPGA_PLL_DIVF_MASK 0x00001FFF macro
43 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
Dclk-pll.c26 #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8 macro
51 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()